Hello.
Please consider the attached suggestions for the sunxi/pinephone
platform.
Among commits written for and by Mobian users, these ones may be of
interest for all pinephone owners.
Each header mentions the original motivation and author.
Thanks.
(Please CC me in follow-ups)
>From 170dde27a95b0cde433dfbe2e5996424c66e8320 Mon Sep 17 00:00:00 2001
From: Arnaud Ferraris
Date: Mon, 24 Feb 2020 11:37:42 +0100
Subject: [PATCH 2/4] pinephone_defconfig: reduce boot delay
On a cellular phone, the vast majority of users can be expected to
have no serial console connected and prefer a short boot.
---
configs/pinephone_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig
index 9967cddab9..9b51a7a100 100644
--- a/configs/pinephone_defconfig
+++ b/configs/pinephone_defconfig
@@ -10,4 +10,5 @@
CONFIG_PINEPHONE_DT_SELECTION=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinephone-1.2"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_BOOTDELAY=0
CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.2"
--
2.20.1
>From 9cc9a9c0131057816d2f7e5a53efc05008d22d6d Mon Sep 17 00:00:00 2001
From: Marius Gripsgard
Date: Tue, 5 May 2020 16:51:13 +0200
Subject: [PATCH 20/20] Enable led on boot to notify user of boot status
---
arch/arm/mach-sunxi/Kconfig | 5 +
board/sunxi/board.c | 4 ++--
configs/pinephone_defconfig | 1 +
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 8421f3b685..2bfdf7738b 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1,5 +1,10 @@
if ARCH_SUNXI
+config PINEPHONE_LEDS
+ bool "Notify boot status via LEDs on PinePhone"
+ ---help---
+ LED boot notification.
+
config SPL_LDSCRIPT
default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index abd7e390b2..a117b89ba2 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -637,6 +638,12 @@ void sunxi_board_init(void)
{
int power_failed = 0;
+#ifdef CONFIG_PINEPHONE_LEDS
+ /* PD18:G PD19:R PD20:B */
+ gpio_request(SUNXI_GPD(18), "led:green");
+ gpio_direction_output(SUNXI_GPD(18), 1);
+#endif
+
#ifdef CONFIG_SY8106A_POWER
power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
#endif
diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig
index ff5da42ce0..9de6ab2316 100644
--- a/configs/pinephone_defconfig
+++ b/configs/pinephone_defconfig
@@ -1,6 +21,7 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
CONFIG_SPL=y
+CONFIG_PINEPHONE_LEDS=y
CONFIG_MACH_SUN50I=y
CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
CONFIG_DRAM_CLK=552
--
2.26.2
>From 26251b8792608080e2e8a551291e8a362cc31769 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng
Date: Fri, 19 Jun 2020 20:16:57 +0800
Subject: [PATCH] sunxi: support asymmetric dual rank DRAM on A64/R40
Previously we have known that R40 has a configuration register for its
rank 1, which allows different configuration than rank 0. Reverse
engineering of newest libdram of A64 from Allwinner shows that A64 has
this register too. It's bit 0 (which enables dual rank in rank 0
configuration register) means a dedicated rank size setup is used for
rank 1.
Now, Pine64 scheduled to use a 3GiB LPDDR3 DRAM chip (which has 2GiB
rank 0 and 1GiB rank 1) on PinePhone, that makes asymmetric dual rank
DRAM support necessary.
Add this support. As we have gained knowledge of asymmetric dual rank,
we can now allow R40 dual rank memory setup to work too.
Signed-off-by: Icenowy Zheng
---
.../include/asm/arch-sunxi/dram_sunxi_dw.h| 11 +-
arch/arm/mach-sunxi/dram_sunxi_dw.c | 100 +-
2 files changed, 84 insertions(+), 27 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
index a5a7ebde44..e843c14202 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
@@ -215,12 +215,17 @@ struct sunxi_mctl_ctl_reg {
#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
/* The eight data lines (DQn) plus DM, DQS and DQSN */
#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3)
-struct dram_para {
+
+struct rank_para {
u16 page_size;
- u8 bus_full_width;
- u8 dual_rank;
u8 row_bits;
u8 bank_bits;
+};
+
+struct dram_para {
+ u8 dual_rank;
+ u8 bus_full_width;
+ struct rank_para ranks[2];
const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
const u8 ac_delays[31];
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index 85e7a1874e..b679f92e70 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -346,18 +346,24 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para)
#else
#error Unsupported DRAM type!
#endif
- (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS
