Helper function for SoCs which use Cortex A7 cpu cores, this should be called
by the SoC's soc_init function to properly setup the cpu core before calling
cpu_init_cp15.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/start.S | 17 +
1 file changed, 17
Replace our current DIY solution for setting the Cortex A7 ACTLR.SMP bit
with using the new soc_init hook and cpu_init_cortex_a7 helper function.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile| 1 +
arch/arm/cpu/armv7/sunxi/board.c | 8
On some SoCs / ARMv7 CPU cores we need to do some setup before enabling the
icache, etc. Add a soc_init hook with a weak default which just calls
cpu_init_cp15.
This way different implementations can be provided to do some extra work
before or after cpu_init_cp15, or completely replacing
Hi Simon,
2015-01-22 1:12 GMT+09:00 Simon Glass s...@chromium.org:
Hi Bin,
On 21 January 2015 at 03:45, Masahiro Yamada yamad...@jp.panasonic.com
wrote:
Hi Simon,
On Mon, 19 Jan 2015 20:12:30 -0700
Simon Glass s...@chromium.org wrote:
diff --git a/common/cmd_i2c.c
On Wed, Jan 21, 2015 at 11:54:08PM +0800, Bin Meng wrote:
+Tom
Hi Tom,
On Mon, Jan 19, 2015 at 9:32 PM, Bin Meng bmeng...@gmail.com wrote:
Remove the additional ',' and '\n' from the gettime command help.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
common/cmd_gettime.c | 4
Currently we've separate detailed dram settings for all sun7i boards, this
moves them over to using auto dram configuration so that we can get rid of
all the per board dram_foo.c files.
This has been tested on a A20-Olinuxino-Lime, A20-Olinuxino_MICRO, Bananapi,
Bananapro, Cubieboard2,
Suriyan Ramasami suriya...@gmail.com writes:
Hello Kevin,
On Tue, Jan 20, 2015 at 3:29 PM, Suriyan Ramasami suriya...@gmail.com wrote:
Hello Kevin,
On Tue, Jan 20, 2015 at 2:43 PM, Kevin Hilman khil...@kernel.org wrote:
Suriyan Ramasami suriya...@gmail.com writes:
Hello Kevin,
These
On 21 January 2015 at 00:38, Heiko Schocher h...@denx.de wrote:
call hw_watchdog_init() also if CONFIG_AT91SAM9_WATCHDOG
is used.
Signed-off-by: Heiko Schocher h...@denx.de
---
common/board_f.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass
On 19 January 2015 at 22:01, Bin Meng bmeng...@gmail.com wrote:
CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this
flag in x86_cpu_init_f() and save it in global data.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/cpu.c | 7 +++
Hi Simon,
On Thu, Jan 22, 2015 at 12:06 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 19 January 2015 at 22:01, Bin Meng bmeng...@gmail.com wrote:
On some x86 processors (like Intel Quark) the MTRR registers are not
supported. This is reflected by the CPUID (EAX 01H) result EDX[12].
Hi Masahiro,
On 21 January 2015 at 10:12, Masahiro YAMADA yamad...@jp.panasonic.com wrote:
Hi Simon,
Yes agreed. I can do that. It seems like the concept is agreed at least.
So how about this:
CONFIG_SPL_STACK_R - bool
CONFIG_SPL_STACK_R _SIZE - hex
Do you need the size of stack? Or
Hello Heiko
here the second part with the real fix and better
commit message.
From 66cdf8324f5e9be1422818cb51c5810b54feef93 Mon Sep 17 00:00:00 2001
From: Anton Habegger anton.habeg...@delta-es.com
Date: Wed, 21 Jan 2015 16:23:02 +0100
Subject: [PATCH] ubifs: Enable journal replay during mount
On 19 January 2015 at 22:01, Bin Meng bmeng...@gmail.com wrote:
arch/x86/cpu/mtrr.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/mtrr.c | 2 ++
1 file changed, 2 insertions(+)
Acked-by: Simon
Hi Bin,
On 21 January 2015 at 03:45, Masahiro Yamada yamad...@jp.panasonic.com wrote:
Hi Simon,
On Mon, 19 Jan 2015 20:12:30 -0700
Simon Glass s...@chromium.org wrote:
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index 1e500fb..7c3ad00 100644
--- a/common/cmd_i2c.c
+++
Hi Bin,
On 19 January 2015 at 22:01, Bin Meng bmeng...@gmail.com wrote:
On some x86 processors (like Intel Quark) the MTRR registers are not
supported. This is reflected by the CPUID (EAX 01H) result EDX[12].
Accessing the MTRR registers on such processors will cause #GP so we
must test the
+Tom
Hi Tom,
On Mon, Jan 19, 2015 at 9:32 PM, Bin Meng bmeng...@gmail.com wrote:
Remove the additional ',' and '\n' from the gettime command help.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
common/cmd_gettime.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Hi Thierry,
On Wed, Jan 21, 2015 at 5:50 PM, Thierry Reding tred...@nvidia.com wrote:
On Tue, Jan 20, 2015 at 06:06:53PM +0100, Sjoerd Simons wrote:
commit a62e84d7b1824a202dd incorrectly changed the tegra pci code to the
new fdtdec pci helpers. To get the device index of the root port, the
I'm trying to load a linux kernel + dtb from the hardware partition boot0 off
an emmc memory.
With the mmc part and mmc dev 1 1 commands i can access the
boot0/boot1/rpmg partitions.
The partitions have been software-partitioned and formatted with fat16
filesystem under linux , kernel and dtb
Hi Thierry,
On Wed, Jan 21, 2015 at 5:40 PM, Thierry Reding tred...@nvidia.com wrote:
On Wed, Jan 21, 2015 at 05:15:42PM +0800, Bin Meng wrote:
Hi Thierry,
On Wed, Jan 21, 2015 at 4:24 PM, Thierry Reding tred...@nvidia.com wrote:
On Wed, Jan 21, 2015 at 10:37:07AM +0800, Bin Meng wrote:
On 19 January 2015 at 20:25, Bin Meng bmeng...@gmail.com wrote:
Various minor code format issues are fixed in start16.S:
- U-boot - U-Boot
- 32bit - 32-bit
- Use TAB instead of SPACE to indent
- Move the indention location of the GDT comment block
Signed-off-by: Bin Meng bmeng...@gmail.com
HI Hans,
On 21 January 2015 at 06:18, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 20-01-15 22:40, Tom Rini wrote:
All of the code in arch/arm/cpu/armv7/sunxi/board.c was under a check
for CONFIG_SPL_BUILD so instead only build for SPL.
That is not true, the #ifdef SPL block ends at
Hi Simon,
On Thu, Jan 22, 2015 at 12:05 AM, Simon Glass s...@chromium.org wrote:
On 19 January 2015 at 22:01, Bin Meng bmeng...@gmail.com wrote:
CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this
flag in x86_cpu_init_f() and save it in global data.
Signed-off-by: Bin Meng
On 21.01.2015 12:55, Graeme Russ wrote:
When booting in JTAG mode, there is no way to use soft break-points, and
no way of knowing when SPL has finished executing (so the user can issue
a 'halt' command to load u-boot.bin for example)
Add a debug output and simple loop to stop execution at the
Hello Heiko
Here the second patch you want. This needs to be applied
prior the real bug fix, becouse it solves the warning as
you mention as well.
From fd0a1377825638d15bc66b5f07a05beb14fe747c Mon Sep 17 00:00:00 2001
From: Anton Habegger anton.habeg...@delta-es.com
Date: Wed, 21 Jan 2015
On Wed, Jan 21, 2015 at 04:24:05PM +0100, Hans de Goede wrote:
2 recent sunxi changes have removed the usage of lowlevel_init by moving some
code around and then setting CONFIG_SKIP_LOWLEVEL_INIT.
This is problematic for 2 reasons:
1) It does not just stop s_init from being called, it also
On 20 January 2015 at 22:16, Joonyoung Shim jy0922.s...@samsung.com wrote:
The dwc3_set_mode function is used only in
drivers/usb/host/xhci-exynos5.c so make it to static.
Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com
---
drivers/usb/host/xhci-exynos5.c | 2 +-
1 file changed, 1
Hello Heiko,
I'll try the patch today. Thank you very much!
Regards,
Konstantyn
-Original Message-
From: Heiko Schocher [mailto:h...@denx.de]
Sent: Wednesday, January 21, 2015 12:57 AM
To: Konstantyn Prokopenko
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] Problem Mounting/Unmounting
The qt840a is one of the many tv-boxes using the i12 A20 pcb, but it
populates only one of the 2 places for a 16 bit dram ic, thus reducing
the buswidth to 16 bits, and the amount of ram to 512M, which is why we
had a separate config for it.
This commit switches the generic i12-tvbox_defconfig
Hi Simon,
Yes agreed. I can do that. It seems like the concept is agreed at least.
So how about this:
CONFIG_SPL_STACK_R - bool
CONFIG_SPL_STACK_R _SIZE - hex
Do you need the size of stack? Or the base address?
But for your particular case, I certainly would like the UART to be
Hi Bin,
On 21 January 2015 at 09:19, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Thu, Jan 22, 2015 at 12:06 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 19 January 2015 at 22:01, Bin Meng bmeng...@gmail.com wrote:
On some x86 processors (like Intel Quark) the MTRR registers are
Hi Masahiro,
On 21 January 2015 at 03:51, Masahiro Yamada yamad...@jp.panasonic.com wrote:
Hi Simon,
On Sun, 18 Jan 2015 11:55:36 -0700
Simon Glass s...@chromium.org wrote:
At present SPL uses a single stack, either CONFIG_SPL_STACK or
CONFIG_SYS_INIT_SP_ADDR. Since some SPL features
On 21 Jan 2015, hdego...@redhat.com wrote:
On some SoCs / ARMv7 CPU cores we need to do some setup before
enabling the icache, etc. Add a soc_init hook with a weak default
which just calls cpu_init_cp15.
This way different implementations can be provided to do some extra
work before or
On Wed, Jan 21, 2015 at 9:55 AM, Graeme Russ gr...@tss-engineering.com wrote:
Signed-off-by: Graeme Russ gr...@tss-engineering.com
It would be nice to have a commit log with the text you put in the
help section that describes the board.
--- /dev/null
+++ b/board/reachtech/g2c1/README
@@ -0,0
On Wed, Jan 21, 2015 at 10:03 AM, Graeme Russ gr...@tss-engineering.com wrote:
Never make simple, last minute changes without testing them...
This should be RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER
I'll fix it in the next version
This looks great, Graeme! Thanks for working on upstream this.
On Wed, Jan 21, 2015 at 9:55 AM, Graeme Russ gr...@tss-engineering.com wrote:
Signed-off-by: Graeme Russ gr...@tss-engineering.com
In the subject I guess you meant 'mxs' instead of mx29.
Also, if you send a v2, please keep Marek on Cc.
___
U-Boot
On Wednesday, January 21, 2015 at 12:55:15 PM, Graeme Russ wrote:
Section 4.1.2 of Freescale Application Note AN4199 describes the
configuration required to operate the mx28 from a 5V source without a
battery. This patch implements the changes to the Freescale bootlets
which allow this
On Wednesday, January 21, 2015 at 12:55:14 PM, Graeme Russ wrote:
Signed-off-by: Graeme Russ gr...@tss-engineering.com
Hi!
- Commit message is missing.
- Some of the debug outputs are missing newline (\n) character
- You can use __func__ and __LINE__ in the debug output to better
specify
On Wednesday, January 21, 2015 at 12:55:18 PM, Graeme Russ wrote:
Signed-off-by: Graeme Russ gr...@tss-engineering.com
Commit message again ;-)
[...]
diff --git a/board/reachtech/g2c1/g2c1.c b/board/reachtech/g2c1/g2c1.c
new file mode 100644
index 000..5bf437d
--- /dev/null
+++
On Wednesday, January 21, 2015 at 12:55:17 PM, Graeme Russ wrote:
mxs_power_clock2pll() does not actually switch the CPU clock to the PLL.
All it does is power-up the PLL and set the CLKCTRL_CLKSEQ_BYPASS_CPU bit
(which was already set by mxs_power_clock2xtal() anyway)
spl_mem_init.c sets up
On Wednesday, January 21, 2015 at 09:53:30 PM, Fabio Estevam wrote:
On Wed, Jan 21, 2015 at 9:55 AM, Graeme Russ gr...@tss-engineering.com
wrote:
Signed-off-by: Graeme Russ gr...@tss-engineering.com
It would be nice to have a commit log with the text you put in the
help section that
Hi Surijan,
Suriyan Ramasami suriya...@gmail.com writes:
Hello Sjoerd Simons,
A signed BL2 which allows unsigned BL2 chain load is already
available for experimentation. Refer this link:
http://forum.odroid.com/viewtopic.php?f=98t=6147#p58984
The suriyan.bl2-hkxu3.1212.5422.zip blob
Hi Heiko,
On 01/21/2015 07:01 PM, Heiko Schocher wrote:
Hello Bo,
Am 21.01.2015 10:45, schrieb Bo Shen:
Supports boot up from NAND flash with software ECC eanbled.
And supports boot up from SD/MMC card with FAT file system.
As the boot from SD/MMC card with FAT file system, the BSS
segment
Hi Igor,
Just kindly remind, did you miss this one? Since you ack the other
patches in this patch set.
On 1/21/2015 7:09 PM, Peng Fan wrote:
This patch add DT support for mxc gpio driver.
There are one place using CONFIG_OF_CONTROL macro.
1. The U_BOOT_DEVICES and mxc_plat array are
Hi Simon,
On Thu, Jan 22, 2015 at 1:02 PM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 21 January 2015 at 21:45, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Thu, Jan 22, 2015 at 11:42 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
In the Baytrail FSP docs I see a note about the
Hello Kevin,
On Wed, Jan 21, 2015 at 4:54 PM, Kevin Hilman khil...@kernel.org wrote:
Hi Surijan,
Suriyan Ramasami suriya...@gmail.com writes:
Hello Sjoerd Simons,
A signed BL2 which allows unsigned BL2 chain load is already
available for experimentation. Refer this link:
On 22/01/15 10:03, Marek Vasut wrote:
On Wednesday, January 21, 2015 at 09:53:30 PM, Fabio Estevam wrote:
On Wed, Jan 21, 2015 at 9:55 AM, Graeme Russ gr...@tss-engineering.com
wrote:
Signed-off-by: Graeme Russ gr...@tss-engineering.com
It would be nice to have a commit log with the text
Fix this:
drivers/pci/pci_rom.c:95:15: warning: cast to pointer from
integer of different size [-Wint-to-pointer-cast]
rom_header = (struct pci_rom_header *)rom_address;
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
drivers/pci/pci_rom.c | 2 +-
1 file changed, 1 insertion(+), 1
only tested tested under QEMU with vexpress_ca9x4 (-M vexpress-a9) and
vexpress_ca15_tc2 (-M vexpress-a15). Makes the ugly warning go away.
Signed-off-by: Chris Kuethe chris.kuethe+git...@gmail.com
---
include/configs/vexpress_common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Hello Anton,
Am 21.01.2015 16:47, schrieb Anton Habegger:
Hello Heiko
Here the second patch you want. This needs to be applied
prior the real bug fix, becouse it solves the warning as
you mention as well.
Thanks, I added Albert Aribaud to Cc, as he is the arm custodian,
and please add such
Hi Simon,
On Thu, Jan 22, 2015 at 11:42 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
In the Baytrail FSP docs I see a note about the HOB passing back the
'Boot Loader Temporary Memory Data HOB'. This seems to be a copy of
the entire temporary memory space. I wonder if we could recover
Hi Bin,
On 21 January 2015 at 21:45, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Thu, Jan 22, 2015 at 11:42 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
In the Baytrail FSP docs I see a note about the HOB passing back the
'Boot Loader Temporary Memory Data HOB'. This seems to be a
Fix this:
warning: cast from pointer to integer of different size
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
drivers/net/e1000.c | 31 +--
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index
Dear Raphael Philipe,
In message caengnhddme5v75wtm+u3w68-zafbtbsrrkfntjfspcypkg1...@mail.gmail.com
you wrote:
I'm working on the improvement of the recipes of u-boot in the Poky
reference system of Yocto project.
Thanks a lot in advance!
My questions are:
- what is the build system
On 22/01/15 10:24, Marek Vasut wrote:
On Wednesday, January 21, 2015 at 12:55:14 PM, Graeme Russ wrote:
Signed-off-by: Graeme Russ gr...@tss-engineering.com
Hi!
- Commit message is missing.
- Some of the debug outputs are missing newline (\n) character
- You can use __func__ and __LINE__
Hi Bin,
In the Baytrail FSP docs I see a note about the HOB passing back the
'Boot Loader Temporary Memory Data HOB'. This seems to be a copy of
the entire temporary memory space. I wonder if we could recover struct
global_data from this?
If so, then we could move the fsp_init stuff to
On some x86 processors (like Intel Quark) the MTRR registers are not
supported. This is reflected by the CPUID (EAX 01H) result EDX[12].
Accessing the MTRR registers on such processors will cause #GP so we
must test the support flag before accessing MTRR MSRs.
Signed-off-by: Bin Meng
CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this
flag in x86_cpu_init_f() and save it in global data.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Changes in v2:
- Use space instead of tab to indent in arch_global_data
arch/x86/cpu/cpu.c | 7 +++
arch/x86/cpu/mtrr.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
---
Changes in v2: None
arch/x86/cpu/mtrr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
On Tuesday, January 20, 2015 at 02:12:41 PM, Peng Fan wrote:
Hi, Marek
On 1/20/2015 7:03 PM, Marek Vasut wrote:
On Friday, December 19, 2014 at 05:39:13 AM, Peng Fan wrote:
If ecc chunk data size is 512 and oobsize is bigger than 512, there is
a chance that block_mark_bit_offset
On Tuesday, January 20, 2015 at 04:23:10 PM, Tom Rini wrote:
On Mon, Jan 19, 2015 at 06:33:43PM +0100, Paul Kocialkowski wrote:
When booting from USB peripheral boot, the bootrom will not properly
deinit the MUSB controller, which doesn't clearly indicate an USB
disconnection to the host
On Tuesday, January 20, 2015 at 11:42:08 PM, Steve Rae wrote:
Implement the UDC support for the USB OTG interface.
Signed-off-by: Steve Rae s...@broadcom.com
---
General question -- this bcm controller you're adding here isn't by
any chance a DWC2 controller, or is it ? There's already a
On Wednesday, January 21, 2015 at 06:16:25 AM, Joonyoung Shim wrote:
The dwc3_set_mode function is used only in
drivers/usb/host/xhci-exynos5.c so make it to static.
Signed-off-by: Joonyoung Shim jy0922.s...@samsung.com
Applied, thanks!
Best regards,
Marek Vasut
On Tuesday, January 20, 2015 at 11:42:06 PM, Steve Rae wrote:
Since a complete gadget implementation is not available yet,
this series provides a method for interfacing the existing gadget
code with the UDC driver code.
Can you please split the series to one patching generic code and one
Hello Heiko
On Thu, Jan 22, 2015 at 7:30 AM, Heiko Schocher h...@denx.de wrote:
Hello Anton,
Am 21.01.2015 16:47, schrieb Anton Habegger:
Hello Heiko
Here the second patch you want. This needs to be applied
prior the real bug fix, becouse it solves the warning as
you mention as well.
On Tue, 20 Jan 2015 14:16:35 +0100
Hans de Goede hdego...@redhat.com wrote:
Hi,
On 20-01-15 09:16, Siarhei Siamashka wrote:
On Mon, 19 Jan 2015 06:29:47 +0200
Siarhei Siamashka siarhei.siamas...@gmail.com wrote:
On Sun, 04 Jan 2015 20:49:38 +0100
Hans de Goede hdego...@redhat.com
Hi Simon,
On Mon, 19 Jan 2015 20:12:36 -0700
Simon Glass s...@chromium.org wrote:
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 23ee771..0682e2e 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -80,6 +80,18 @@ int device_bind(struct udevice *parent,
Hello Simon, Masahiro,
Am 21.01.2015 16:51, schrieb Simon Glass:
Hi Masahiro,
On 21 January 2015 at 03:51, Masahiro Yamada yamad...@jp.panasonic.com wrote:
Hi Simon,
On Sun, 18 Jan 2015 11:55:36 -0700
Simon Glass s...@chromium.org wrote:
At present SPL uses a single stack, either
On Tue, 20 Jan 2015 15:43:31 +0100
Hans de Goede hdego...@redhat.com wrote:
Hi,
On 19-01-15 21:16, Priit Laes wrote:
Gemei G9 is an A10 based tablet, with 1G RAM, 16G NAND, 1024x768
IPS LCD display, stereo speakers, 1.3MP front camera and 5 MP
rear camera, 8000mAh battery, GT901 2+1
Signed-off-by: Graeme Russ gr...@tss-engineering.com
---
arch/arm/Kconfig | 13 ++
board/reachtech/g2c1/Kconfig | 15 ++
board/reachtech/g2c1/MAINTAINERS | 9 +
board/reachtech/g2c1/Makefile| 12 ++
board/reachtech/g2c1/README | 58 +
Section 4.1.2 of Freescale Application Note AN4199 describes the
configuration required to operate the mx28 from a 5V source without a
battery. This patch implements the changes to the Freescale bootlets
which allow this configuration to properly boot the mx28 processor
Signed-off-by: Graeme Russ
When booting in JTAG mode, there is no way to use soft break-points, and
no way of knowing when SPL has finished executing (so the user can issue
a 'halt' command to load u-boot.bin for example)
Add a debug output and simple loop to stop execution at the completion of
the SPL initialisation as a
mxs_power_clock2pll() does not actually switch the CPU clock to the PLL.
All it does is power-up the PLL and set the CLKCTRL_CLKSEQ_BYPASS_CPU bit
(which was already set by mxs_power_clock2xtal() anyway)
spl_mem_init.c sets up the fractional divisor (which is required to run
the CPU from the PLL)
On 01/21/15 13:09, Peng Fan wrote:
Signed-off-by: Peng Fan peng@freescale.com
I think this should be a part of the first patch, anyway:
Acked-by: Igor Grinberg grinb...@compulab.co.il
---
include/dm/device.h | 9 +
1 file changed, 9 insertions(+)
diff --git
Hi Simon,
On Mon, 19 Jan 2015 20:12:30 -0700
Simon Glass s...@chromium.org wrote:
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index 1e500fb..7c3ad00 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -168,7 +168,7 @@ static int i2c_get_cur_bus_chip(uint chip_addr, struct
Hello Bo,
Am 21.01.2015 10:45, schrieb Bo Shen:
Supports boot up from NAND flash with software ECC eanbled.
And supports boot up from SD/MMC card with FAT file system.
As the boot from SD/MMC card with FAT file system, the BSS
segment is too big to fit into SRAM, so, use the lds to put
it into
This patch set is to add DT support for mxc_gpio driver.
patch 1/4 and 2/4, a new dev_get_addr interface is abstracted to
improve driver who want to get device address.
patch 3/4, add a new bank_index entry in platdata to avoid `plat - mxc_plat`
pointer subtract
This patch add DT support for mxc gpio driver.
There are one place using CONFIG_OF_CONTROL macro.
1. The U_BOOT_DEVICES and mxc_plat array are complied out. To DT,
platdata is alloced using calloc, so there is no need to use mxc_plat.
The following situations are tested, and all work fine:
1.
Add a new entry in platdata structure and intialize
bank_index in mxc_plat array.
This new entry can avoid using `plat - mxc_plat` by using
`plat-bank_index`.
Signed-off-by: Peng Fan peng@freescale.com
---
drivers/gpio/mxc_gpio.c | 17 +
1 file changed, 9 insertions(+), 8
Signed-off-by: Graeme Russ gr...@tss-engineering.com
---
arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 1 +
arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c | 13 +++-
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 18 +
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 100
This series adds support for booting mx28 based boards which do not
include a battery as per Freescale application note AN4199
Patch 2 (which implements booting without a battery) is based on a patch
submitted to the Freescale community forums by Damien Gotfroi (Cc'd)
The patch series adds the
On 01/21/15 13:09, Peng Fan wrote:
Abstracting dev_get_addr can improve drivers that want to
get device's address.
Signed-off-by: Peng Fan peng@freescale.com
Acked-by: Igor Grinberg grinb...@compulab.co.il
--
Regards,
Igor.
___
U-Boot
Hi Igor,
On 1/21/2015 5:18 PM, Igor Grinberg wrote:
[...]
@@ -295,12 +282,77 @@ static int mxc_gpio_probe(struct udevice *dev)
return 0;
}
+#ifdef CONFIG_OF_CONTROL
+static struct gpio_regs *mxc_get_gpio_addr(struct udevice *device)
+{
+fdt_addr_t addr;
+addr =
Hi Simon,
On Sun, 18 Jan 2015 11:55:36 -0700
Simon Glass s...@chromium.org wrote:
At present SPL uses a single stack, either CONFIG_SPL_STACK or
CONFIG_SYS_INIT_SP_ADDR. Since some SPL features (such as MMC and
environment) require a lot of stack, some boards set CONFIG_SPL_STACK to
point
update SPL WDT support and use it on the taurus board
- if CONFIG_AT91SAM9_WATCHDOG is set:
- do not disable WDT in SPL
- call hw_watchdog_init()
- make the WDT timeout configurable
- enable it on the taurus board
Heiko Schocher (4):
arm, at91, wdt: do not disable WDT in SPL
On Tue, 2015-01-20 at 16:40 -0500, Tom Rini wrote:
In general the change looks good, thanks.
-#if !defined CONFIG_SPL_BUILD (defined CONFIG_MACH_SUN7I || \
- defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
- /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary
Abstracting dev_get_addr can improve drivers that want to
get device's address.
Signed-off-by: Peng Fan peng@freescale.com
---
drivers/core/device.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 963b16f..0ba5c76
Signed-off-by: Peng Fan peng@freescale.com
---
include/dm/device.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/include/dm/device.h b/include/dm/device.h
index 13598a1..ee00c4d 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -322,4 +322,13 @@ int
On 01/21/15 13:09, Peng Fan wrote:
Add a new entry in platdata structure and intialize
bank_index in mxc_plat array.
This new entry can avoid using `plat - mxc_plat` by using
`plat-bank_index`.
Signed-off-by: Peng Fan peng@freescale.com
Acked-by: Igor Grinberg grinb...@compulab.co.il
remove MACH_TYPE definitions in config file, as they come from
the defconfig.
Signed-off-by: Heiko Schocher h...@denx.de
---
include/configs/taurus.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index b61dc2d..2cf4558 100644
---
Hi Heiko,
On 01/21/2015 03:42 PM, Heiko Schocher wrote:
add reset controller status register
Signed-off-by: Heiko Schocher h...@denx.de
Acked-by: Bo Shen voice.s...@atmel.com
---
arch/arm/include/asm/arch-at91/at91_rstc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
On Wed, 2015-01-21 at 09:24 +0100, Thierry Reding wrote:
On Wed, Jan 21, 2015 at 10:37:07AM +0800, Bin Meng wrote:
Hi,
On Wed, Jan 21, 2015 at 3:05 AM, Simon Glass s...@chromium.org wrote:
Hi Sjoerd,
On 20 January 2015 at 10:06, Sjoerd Simons
sjoerd.sim...@collabora.co.uk
Hi Tom,
please pull these 3 patches to your tree. On patch is fixing gem.
One is fixing ll_temac which you have reported and the last one is for MMC.
I have created special branch just with these changes.
Thanks,
Michal
The following changes since commit
The patch enables and adds PCIe settings for boards LS1021AQDS
and LS1021ATWR.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
include/configs/ls1021aqds.h | 24
include/configs/ls1021atwr.h | 24
2 files changed, 48 insertions(+)
On Tue, Jan 20, 2015 at 06:06:53PM +0100, Sjoerd Simons wrote:
commit a62e84d7b1824a202dd incorrectly changed the tegra pci code to the
new fdtdec pci helpers. To get the device index of the root port, the
reg property should be parsed from the dtb (as was previously the
case).
With this
On Wed, Jan 21, 2015 at 10:00:39AM +0800, Bin Meng wrote:
Hi Simon,
On Tue, Jan 20, 2015 at 10:31 PM, Simon Glass s...@chromium.org wrote:
+Thierry
Hi Bin,
On 20 January 2015 at 05:59, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Jan 20, 2015 at 11:19 AM, Simon Glass
On Tue, Jan 20, 2015 at 12:05:40PM -0700, Simon Glass wrote:
Hi Sjoerd,
On 20 January 2015 at 10:06, Sjoerd Simons
sjoerd.sim...@collabora.co.uk wrote:
commit a62e84d7b1824a202dd incorrectly changed the tegra pci code to the
new fdtdec pci helpers. To get the device index of the root
On Mon, 2015-01-19 at 20:19 -0700, Simon Glass wrote:
In commit a62e84d the old functionality of obtaining a PCI address from the
'reg' property was lost. Add it back, so we can support both a compatible
string list and a 'reg' property.
This patch fixes PCIe ethernet on Tegra boards.
On Wed, Jan 21, 2015 at 04:46:42PM +0800, Bin Meng wrote:
Hi Thierry,
On Wed, Jan 21, 2015 at 4:05 PM, Thierry Reding tred...@nvidia.com wrote:
On Wed, Jan 21, 2015 at 10:00:39AM +0800, Bin Meng wrote:
Hi Simon,
On Tue, Jan 20, 2015 at 10:31 PM, Simon Glass s...@chromium.org wrote:
On Wed, Jan 21, 2015 at 05:15:42PM +0800, Bin Meng wrote:
Hi Thierry,
On Wed, Jan 21, 2015 at 4:24 PM, Thierry Reding tred...@nvidia.com wrote:
On Wed, Jan 21, 2015 at 10:37:07AM +0800, Bin Meng wrote:
Hi,
On Wed, Jan 21, 2015 at 3:05 AM, Simon Glass s...@chromium.org wrote:
Hi
On 21.01.2015 00:51, Dinh Nguyen wrote:
On 01/14/2015 05:34 PM, Marek Vasut wrote:
On Wednesday, January 14, 2015 at 05:40:41 PM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Hi!
This adds the code to configure the SDRAM controller that is found in
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