The Atmel AT97SC3204 is also TIS compliant.
Modify the tpm_tis_lpc driver to check for the vid/did used by the
Atmel AT97SC3204 and report an appropriate description.
Signed-off-by: George McCollister
---
drivers/tpm/tpm_tis_lpc.c | 37
Previously it was believed L3 cache has to be flushed in order to guarantee
data integrity in main memory. However, flushing L3 cache may require EL3,
depending on SoC implementation. Flushing with virtual address can also
put data into main memory. The trick is to find the correct address range.
On 10/14/2016 01:01 PM, York Sun wrote:
> Previously it was believed L3 cache has to be flushed in order to guarantee
> data integrity in main memory. However, flushing L3 cache may require EL3,
> depending on SoC implementation. Flushing with virtual address can also
> put data into main memory.
On Thu, Oct 13, 2016 at 04:53:40PM -0600, Simon Glass wrote:
> Hi Tom,
>
> Here is a second attempt with this patch pulled in:
>
> http://patchwork.ozlabs.org/patch/681814/
>
>
> The following changes since commit c69f6d04ec66433f2360490a5cd0263c83aab18f:
>
> Merge branch 'master' of
I have been puzzled by the need to flush external L3 cache for Freescale
Layerscape series SoCs. Flushing L3 requires EL3. It is the case now, but
this may change in the future. Implementing a SMC call to perform this
task is possible but only if necessary. Recent investigation shows we can
flush
Current code turns off d-cache first, then flush all levels of cache.
This results data loss. As soon as d-cache is off, the dirty cache
is discarded according to the test on LS2080A. This issue was not
seen as long as external L3 cache was flushed to push the data to
main memory. However,
Current code turns off d-cache first, then flush all levels of cache.
This results data loss. As soon as d-cache is off, the dirty cache
is discarded according to the test on LS2080A. This issue was not
seen as long as external L3 cache was flushed to push the data to
main memory. However,
Previously it was believed L3 cache has to be flushed in order to guarantee
data integrity in main memory. However, flushing L3 cache may require EL3,
depending on SoC implementation. Flushing with virtual address can also
put data into main memory. The trick is to find the correct address range.
I have been puzzled by the need to flush external L3 cache for Freescale
Layerscape series SoCs. Flushing L3 requires EL3. It is the case now, but
this may change in the future. Implementing a SMC call to perform this
task is possible but only if necessary. Recent investigation shows we can
flush
On 10/14/2016 02:17 PM, York Sun wrote:
Current code turns off d-cache first, then flush all levels of cache.
This results data loss. As soon as d-cache is off, the dirty cache
is discarded according to the test on LS2080A. This issue was not
seen as long as external L3 cache was flushed to push
On 10/14/2016 01:30 PM, Stephen Warren wrote:
> On 10/14/2016 02:17 PM, York Sun wrote:
>> Previously it was believed L3 cache has to be flushed in order to guarantee
>> data integrity in main memory. However, flushing L3 cache may require EL3,
>> depending on SoC implementation. Flushing with
On 10/14/2016 02:17 PM, York Sun wrote:
Previously it was believed L3 cache has to be flushed in order to guarantee
data integrity in main memory. However, flushing L3 cache may require EL3,
depending on SoC implementation. Flushing with virtual address can also
put data into main memory. The
On 10/10/2016 10:52 AM, Dinh Nguyen wrote:
> Hi,
>
> This patchset adds the PL330 DMA driver to U-Boot. The SoCFPGA platform makes
> use of the PL330 to transfer zereos to the SDRAM which enables the ECC bit.
>
> This is only an RFC because after rebasing to v2016.11-rc1, I had to revert
> the
On 10/14/2016 10:09 AM, Marek Vasut wrote:
> On 10/14/2016 03:08 PM, Dinh Nguyen wrote:
>>
>>
>> On 10/14/2016 02:23 AM, Marek Vasut wrote:
>>> On 10/10/2016 05:52 PM, Dinh Nguyen wrote:
Hi,
>>>
>>> Hi,
>>>
This patchset adds the PL330 DMA driver to U-Boot. The SoCFPGA platform
On Thu, Oct 13, 2016 at 9:10 PM, Masahiro Yamada
wrote:
> ARCH_SUNXI selects DM_USB, where CONFIG_USB_MAX_CONTROLLER_COUNT
> is not used.
>
> Signed-off-by: Masahiro Yamada
> ---
Reviewed-by: Jagan Teki
thanks!
Hi Uboot team,
Is this problem of EHCI timed out on TD - token=0x80008d80 already resolved
?
If yes can soneone please point me to the solution.
I am seeing this read timeout failure with 2 n 4 GB Usb drives.
Its a no go for our project, please help or advise.
Thanks,
Mike
On Fri, Oct 14, 2016 at 10:54 AM, Vignesh R wrote:
> Hi,
>
> On Thursday 13 October 2016 05:41 PM, Jagan Teki wrote:
>> On Wed, Oct 12, 2016 at 9:46 AM, Vignesh R wrote:
>>> Fix the divider calculation logic to choose a value so that the
>>> resulting baudrate
Hello hi, my name is jean-philippe theroux.
i'm rather new to linux and tonight i had the crazy idea to try to
recompile the kernel on a orange pi plus Soc.
i am using a somewhat recent distribution and i believe it's not even been
released with the actual config and all the fixes i made (to the
On 10/14/2016 12:27 PM, Jagan Teki wrote:
> On Fri, Oct 14, 2016 at 10:54 AM, Vignesh R wrote:
...
DECLARE_GLOBAL_DATA_PTR;
@@ -118,7 +119,7 @@ static void ti_spi_set_speed(struct ti_qspi_priv
*priv, uint hz)
if (!hz)
Fix the divider calculation logic to choose a value so that the
resulting baudrate is either equal to or closest possible baudrate less
than the requested value. While at that, cleanup ti_spi_set_speed().
Signed-off-by: Vignesh R
---
v2: cleanup ti_spi_set_speed() a bit.
do not apply this patches to mainline!
I move the patches to my ToDo list, until a tbot
patchwork user is created.
This is for a simple test to create a tbot demo video, which
will demonstrate:
- Step 1:
- clone mainline u-boot, compile, install it on
a board, and start a simple uboot
do not apply this patch to mainline, simple test for
a tbot demo, please ignore.
Signed-off-by: Heiko Schocher
do not apply this patch to mainline, simple test for
a tbot demo.
---
README | 2 ++
1 file changed, 2 insertions(+)
diff --git a/README b/README
index
do not apply this patch to mainline, simple test for
a tbot demo, please ignore.
Signed-off-by: Heiko Schocher
---
README | 1 +
1 file changed, 1 insertion(+)
diff --git a/README b/README
index 50e53a1..5cb82f7 100644
--- a/README
+++ b/README
@@ -6,6 +6,7 @@
#
Test
+Test 2
do not apply this patch to mainline, simple test for
a tbot demo, please ignore.
Signed-off-by: Heiko Schocher
---
README | 1 +
1 file changed, 1 insertion(+)
diff --git a/README b/README
index 1f56fdc..adfdf1a 100644
--- a/README
+++ b/README
@@ -11,6 +11,7 @@ Test 3
Test 4
Hi Stefan,
> Instead of creating a journal entry for each directory block, even
> if the block is unmodified, only log the modified block.
>
> Signed-off-by: Stefan Brüns
> ---
> fs/ext4/ext4_common.c | 23 +--
> 1 file changed, 13
On Fri, Oct 14, 2016 at 9:29 AM, Michal Simek wrote:
> On 13.10.2016 17:40, Masahiro Yamada wrote:
>> ARCH_ZYNQ(MP) selects DM_USB, where CONFIG_USB_MAX_CONTROLLER_COUNT
>> is not used.
>>
>> Signed-off-by: Masahiro Yamada
>> ---
>>
>>
Hi Stefan,
> The direntlen checks were quite bogus, i.e. the loop termination used
> "len + offset == blocksize" (exact match only), and checked for a
> direntlen less than 0. The latter can never happen as the len is
> unsigned, this has been reported by Coverity, CID 153384.
>
> Use the same
Hi,
Le 14/10/2016 à 01:00, Joe Hershberger a écrit :
On Fri, Oct 14, 2016 at 12:52 AM, Simon Glass wrote:
Hi Tom,
On 13 October 2016 at 13:11, Tom Rini wrote:
Hey all,
I've noticed now, but not dug into a problem that goes like this. On
every
On 13.10.2016 17:40, Masahiro Yamada wrote:
> ARCH_ZYNQ(MP) selects DM_USB, where CONFIG_USB_MAX_CONTROLLER_COUNT
> is not used.
>
> Signed-off-by: Masahiro Yamada
> ---
>
> include/configs/xilinx_zynqmp.h | 1 -
> include/configs/zynq-common.h | 1 -
> 2 files
do not apply this patch to mainline, simple test for
a tbot demo, please ignore.
Signed-off-by: Heiko Schocher
---
README | 1 +
1 file changed, 1 insertion(+)
diff --git a/README b/README
index 812febb..cf98e7c 100644
--- a/README
+++ b/README
@@ -8,6 +8,7 @@
Test
Test 2
do not apply this patch to mainline, simple test for
a tbot demo, please ignore.
Signed-off-by: Heiko Schocher
---
README | 1 +
1 file changed, 1 insertion(+)
diff --git a/README b/README
index 2305a77..1f56fdc 100644
--- a/README
+++ b/README
@@ -10,6 +10,7 @@ Test 2
Test 3
do not apply this patch to mainline, simple test for
a tbot demo, please ignore.
Signed-off-by: Heiko Schocher
---
README | 1 +
1 file changed, 1 insertion(+)
diff --git a/README b/README
index adfdf1a..921d79d 100644
--- a/README
+++ b/README
@@ -12,6 +12,7 @@ Test 4
Test 5
do not apply this patch to mainline, simple test for
a tbot demo, please ignore.
Signed-off-by: Heiko Schocher
---
README | 1 +
1 file changed, 1 insertion(+)
diff --git a/README b/README
index cf98e7c..2305a77 100644
--- a/README
+++ b/README
@@ -9,6 +9,7 @@ Test
Test 2
Test
do not apply this patch to mainline, simple test for
a tbot demo, please ignore.
Signed-off-by: Heiko Schocher
---
cmd/help.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/help.c b/cmd/help.c
index 701ae7e..d58bbdd 100644
--- a/cmd/help.c
+++
do not apply this patch to mainline, simple test for
a tbot demo, please ignore.
Signed-off-by: Heiko Schocher
---
README | 1 +
1 file changed, 1 insertion(+)
diff --git a/README b/README
index 5cb82f7..812febb 100644
--- a/README
+++ b/README
@@ -7,6 +7,7 @@
Test
Test 2
On 10/10/2016 05:52 PM, Dinh Nguyen wrote:
> Hi,
Hi,
> This patchset adds the PL330 DMA driver to U-Boot. The SoCFPGA platform makes
> use of the PL330 to transfer zereos to the SDRAM which enables the ECC bit.
Is there some considerable performance benefit over memset() in this case ?
> This
Hey guys,
After making Stephen's scripts work with qemu today, I've started
testing out what platforms I can test out via qemu. I've found two
problems with qemu-x86. First, there's a real problem with the network.
I run qemu with "-nographic -cpu qemu32 -netdev
user,id=net0,tftp=/tftpboot
>From: Bin Meng [mailto:bmeng...@gmail.com]
>On Fri, Oct 14, 2016 at 1:49 PM, Sriram Dash wrote:
>> Defines get_svr() for mpc512x devices
>>
>> Signed-off-by: Sriram Dash
>> ---
>> arch/powerpc/cpu/mpc512x/start.S | 5 +
>> 1 file changed, 5
On Mon, Sep 19, 2016 at 01:59:44PM +0200, Andreas Reichel wrote:
> Hi Tom,
>
> is my patch going to be applied or is the problem resolved
> otherwhise?
Sorry, lost in my patchwork queue. I'll pick this up soon now.
>
> Kind regards
> Andreas
>
> On Mo, Sep 05, 2016 at 07:04:53 -0600,
On Fri, Oct 14, 2016 at 11:13:11AM +0200, Guillaume Gardet wrote:
> Hi,
>
>
> Le 14/10/2016 à 01:00, Joe Hershberger a écrit :
> >On Fri, Oct 14, 2016 at 12:52 AM, Simon Glass wrote:
> >>Hi Tom,
> >>
> >>On 13 October 2016 at 13:11, Tom Rini wrote:
>
Joe,
On 02/09/16 17:53, Tom Rini wrote:
> On Wed, Aug 24, 2016 at 03:35:49PM +0300, Roger Quadros wrote:
>
>> From: Mugunthan V N
>>
>> cpsw driver supports only selection of phy mode in control module
>> but control module has more setting like RGMII ID mode selection,
>>
On 10/14/2016 02:23 AM, Marek Vasut wrote:
> On 10/10/2016 05:52 PM, Dinh Nguyen wrote:
>> Hi,
>
> Hi,
>
>> This patchset adds the PL330 DMA driver to U-Boot. The SoCFPGA platform makes
>> use of the PL330 to transfer zereos to the SDRAM which enables the ECC bit.
>
> Is there some
Hi everyone,
I'm trying to boot u-boot from uEnv.txt. And I've got a problem. I'm
using zynq_picozed_defconfig
The problem is I've got this error after the uEnv.txt is read:
---
...
eth0: ethernet@e000b000
Hit any key to stop autoboot: 0
Device: sdhci@e010
Manufacturer
Le jeudi 13 octobre 2016 à 13:47 +0300, Nicolae Rosia a écrit :
> From: Nicolae Rosia
>
> Commit a85362fb3e1fc7833723accddbbae431091d06b8 refactored the code
> but the register read ended up in the wrong if branch.
> Currently, the else branch checks a variable which is
On 10/14/2016 03:08 PM, Dinh Nguyen wrote:
>
>
> On 10/14/2016 02:23 AM, Marek Vasut wrote:
>> On 10/10/2016 05:52 PM, Dinh Nguyen wrote:
>>> Hi,
>>
>> Hi,
>>
>>> This patchset adds the PL330 DMA driver to U-Boot. The SoCFPGA platform
>>> makes
>>> use of the PL330 to transfer zereos to the
Compiler attributes are more commonly __foo style tags rather than big
upper case eye sores like EFI_RUNTIME_TEXT.
Simon Glass felt quite strongly about this, so this patch converts our
existing defines over to more eye friendly ones.
Signed-off-by: Alexander Graf
---
On Fri, Oct 14, 2016 at 10:35:23AM +0530, Lokesh Vutla wrote:
> Early system initialization is being done before initf_dm is being called
> in U-Boot. Then system will fail to boot if any of the DM enabled driver
> is being called in this system initialization code. So, rearrange the
> code a bit
On 10/10/2016 05:52 PM, Dinh Nguyen wrote:
> From: Dinh Nguyen
>
> Add PL330_DMA entry.
>
> Signed-off-by: Dinh Nguyen
This should be wrapped into 1/4
> ---
> drivers/dma/Kconfig | 4
> drivers/dma/Makefile | 1 +
> 2
On 10/10/2016 05:52 PM, Dinh Nguyen wrote:
> From: Dinh Nguyen
>
> Add DMA_SUPPORTS_DEV_TO_MEM type to the DMA uclass.
>
> Signed-off-by: Dinh Nguyen
> ---
> drivers/dma/dma-uclass.c | 3 ++-
> 1 file changed, 2 insertions(+), 1
On Fri, Oct 14, 2016 at 10:35:25AM +0530, Lokesh Vutla wrote:
> Detect the board very early and avoid reading eeprom multiple times.
>
> Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
--
Tom
signature.asc
Description: Digital signature
On Fri, Oct 14, 2016 at 10:35:24AM +0530, Lokesh Vutla wrote:
> This is similar to Commit 93e6253d11030 ("ARM: OMAP4/5: Centralize
> early clock initialization") that was done for OMAP4+, reflecting the same
> for AM33xx and AM43xx SoCs to centralize clock initialization.
>
> Signed-off-by:
On Mon, Sep 26, 2016 at 02:21:30PM +0900, Masahiro Yamada wrote:
> Jon Master reports that QEMU refuses to load a U-Boot image built
> with CONFIG_ARMV7_NONSEC, but without CONFIG_ARMV7_PSCI since
> commit 5a3aae68c74e ("ARM: armv7: guard memory reserve for PSCI
> with #ifdef CONFIG_ARMV7_PSCI").
On Fri, Oct 14, 2016 at 07:13:01PM -0400, Tom Rini wrote:
> We can only run this command if the sleep command is enabled and that
> depends on CONFIG_CMD_MISC
>
> Signed-off-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital
We can only run this command if the sleep command is enabled and that
depends on CONFIG_CMD_MISC
Signed-off-by: Tom Rini
---
test/py/tests/test_sleep.py | 2 ++
1 file changed, 2 insertions(+)
diff --git a/test/py/tests/test_sleep.py b/test/py/tests/test_sleep.py
index
Defines get_svr() for mpc512x devices
Signed-off-by: Sriram Dash
---
arch/powerpc/cpu/mpc512x/start.S | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/cpu/mpc512x/start.S b/arch/powerpc/cpu/mpc512x/start.S
index 471d401..2507842 100644
---
On Fri, Oct 14, 2016 at 1:49 PM, Sriram Dash wrote:
> Defines get_svr() for mpc512x devices
>
> Signed-off-by: Sriram Dash
> ---
> arch/powerpc/cpu/mpc512x/start.S | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git
Defines get_svr() for mpc512x devices
Signed-off-by: Sriram Dash
Reviewed-by: Bin Meng
---
Changes in v2:
- cosmetic changes
arch/powerpc/cpu/mpc512x/start.S | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/cpu/mpc512x/start.S
On 10/12/2016 08:00 PM, York Sun wrote:
> On 10/11/2016 08:00 PM, Yao Yuan wrote:
> >>
> >> Yuan Yao,
> >>
> >> I think the procedure can be applied to many of our boards with QSPI,
> >> right? It may be better to move this information out of ls2080aqds.
> >>
> >
> > Hi York,
> >
> > Yes, but a
On 10/14/2016 07:21 AM, Bin Meng wrote:
On Fri, Oct 14, 2016 at 1:13 PM, Alexander Graf wrote:
Am 14.10.2016 um 03:50 schrieb Bin Meng :
On Thu, Oct 13, 2016 at 10:35 PM, Alexander Graf wrote:
The type 4 table generation code is very x86
On 10/13/2016 11:45 PM, Yao Yuan wrote:
> On 10/12/2016 08:00 PM, York Sun wrote:
>> On 10/11/2016 08:00 PM, Yao Yuan wrote:
Yuan Yao,
I think the procedure can be applied to many of our boards with QSPI,
right? It may be better to move this information out of ls2080aqds.
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