Based on latest hardware documentation,
update ccsr_gur structure (represents DCFG register map)
Signed-off-by: Priyanka Jain
Signed-off-by: Arpit Goel
---
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 65 ++--
1 files
Move all of the status LED feature to drivers/led/Kconfig.
The LED status definitions were moved from the board configuration
files to the defconfig files.
TBD: Move all of the definitions in the include/status_led.h to the
relevant board's defconfig files.
Tested boards: CL-SOM-AM57x, CM-T335
Move all of the status LED feature to drivers/led/Kconfig.
doc/README.LED updated to reflect the Kconfig implementation.
Tested boards: CL-SOM-AM57x, CM-T335
Signed-off-by: Uri Mashiach
---
README | 8 +-
doc/README.LED | 58 +-
Hi,
no ideas ?
I can try another solution if you want.
Regards,
Romain
Le 09/01/2017 à 09:23, Romain Perier a écrit :
Hi,
Le 09/01/2017 à 08:20, Kever Yang a écrit :
On 01/06/2017 06:52 PM, Romain Perier wrote:
Add Rockchip Engineers to Cc:
Le 06/01/2017 à 11:28, Romain Perier a
Hi Stefan,
On 01/17/2017 11:58 PM, stefan.herbrechtsme...@weidmueller.com wrote:
> From: Stefan Herbrechtsmeier
>
> The sdhci controller assumes that the base clock frequency is fully supported
> by
> the peripheral and doesn't support hardware
Instead of disabling the data cache in the bootelf command, disabling
it in the do_bootm_qnxelf function.
Some ELF binary might want the cache enabled.
Signed-off-by: Emmanuel Vadot
---
cmd/elf.c | 11 ---
common/bootm_os.c | 12
2 files
Hi,
On 01/10/2017 07:18 PM, Jagan Teki wrote:
> From: Jagan Teki
>
> Print the error code for non-zero (failure case) instead
> of making debug statement without any condition, this
> usually gives proper clue in failure condition.
>
> Log:
> ---
> MMC: FSL_SDHC:
Currently maximum volume size can be specified only if no other
arguments are used. Use '-' placeholder as volume size to allow
maximum volume size to be specified together with volume id and
type.
Signed-off-by: Ladislav Michl
---
cmd/ubi.c | 8 +---
1 file changed, 5
Hi Adam,
On 01/12/2017 06:07 AM, Adam Ford wrote:
> On the OMAP36xx (and 37xx) the CONTROL_WKUP_CTRL register has
> a field (bit 6) named GPIO_IO_PWRDNZ. If 0, the IO buffers which
> are related to the MMC are disabled. After the PBIAS is configured,
> this bit should be set high to enable the
On 01/18/2017 12:27 AM, stefan.herbrechtsme...@weidmueller.com wrote:
> From: Stefan Herbrechtsmeier
>
> The maximum supported peripheral clock frequency of the zynq depends on
> the IO routing. The MIO and EMIO support a maximum frequency of 50 MHz
>
On 01/18/2017 12:27 AM, stefan.herbrechtsme...@weidmueller.com wrote:
> From: Stefan Herbrechtsmeier
>
> The zynq_sdhci controller driver use CONFIG_ZYNQ_SDHCI_MAX_FREQ as base
> clock frequency but this clock is not fixed and depends on the hardware
>
Hi.
(CCing Simon because he wrote the code addressed in this discussion.)
2017-01-17 18:27 GMT+09:00 Oded Gabbay :
> Hi Mashiro,
> Could you please also take a look at the patch I sent to add the
> missing __bss_size ?
>
> Thanks,
> Oded
>
> On Mon, Dec 26, 2016 at 4:20
2017-01-17 18:20 GMT+09:00 Oded Gabbay :
> On Tue, Jan 17, 2017 at 11:07 AM, Masahiro Yamada
> wrote:
>> 2017-01-16 3:30 GMT+09:00 Tom Rini :
>>> On Wed, Dec 28, 2016 at 01:38:35PM +0200, Oded Gabbay wrote:
>>>
When
On Thu, Jan 19, 2017 at 2:07 PM, Masahiro Yamada
wrote:
> This feature seems to be sometimes misunderstood. The intention is
>
> [1] Bring the slaves into U-Boot proper image, not SPL (unless
> you have a special reason).
>
> [2] The operation must be done in a
On Thu, Jan 19, 2017 at 2:22 PM, Masahiro Yamada
wrote:
> 2017-01-17 18:20 GMT+09:00 Oded Gabbay :
>> On Tue, Jan 17, 2017 at 11:07 AM, Masahiro Yamada
>> wrote:
>>> 2017-01-16 3:30 GMT+09:00 Tom Rini
>> For your information, my own code for spin-table is
>> arch/arm/mach-uniphier/smp_kick_cpus.c
>> this is called from board_init().
>>
> Thanks for the tip, I'll take a look.
I meant
arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
--
Best Regards
Masahiro Yamada
This feature seems to be sometimes misunderstood. The intention is
[1] Bring the slaves into U-Boot proper image, not SPL (unless
you have a special reason).
[2] The operation must be done in a board (SoC) specific manner
since how to wake the slaves from the Boot ROM is SoC specific.
Hi,
On 01/19/2017 05:53 AM, Rask Ingemann Lambertsen wrote:
> The execution flow is currently like this for aldo_num == 1 or 2:
>
> int axp_set_aldo(int aldo_num, unsigned int mvolt)
> {
> ...
> if (mvolt == 0)
> return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
>
On 8 January 2017 at 22:47, Jaehoon Chung wrote:
> Use the node's name for i2c.
>
> Signed-off-by: Jaehoon Chung
> ---
> arch/arm/dts/exynos4.dtsi | 27 +++
> 1 file changed, 19 insertions(+), 8 deletions(-)
Reviewed-by:
Hi Jaehoon,
On 8 January 2017 at 22:47, Jaehoon Chung wrote:
> Revmoe the "ifndef CONFIG_DM_I2C".
> Intead, use the driver model for max8998.
>
> Signed-off-by: Jaehoon Chung
> ---
> board/samsung/universal_c210/universal.c | 169
>
On 8 January 2017 at 22:47, Jaehoon Chung wrote:
> Adding Kconfig for SYS_I2C_S3C24X0.
>
> Signed-off-by: Jaehoon Chung
> ---
> drivers/i2c/Kconfig | 5 +
> 1 file changed, 5 insertions(+)
Reviewed-by: Simon Glass
Hi,
On 18 January 2017 at 09:23, Stefan Roese wrote:
> On 11.01.2017 16:00, Mario Six wrote:
>>
>> On boards that use DM, it is sometimes convenient and quicker to get a
>> device
>> via its device tree path, since the devices used in the board
>> initialization
>> routines are
On 8 January 2017 at 22:47, Jaehoon Chung wrote:
> If CONFIG_SYS_I2C_S3C24X0_SLAVE isn't defined, then complie error should
> be occurred.
> This patch is for preventing it.
>
> Signed-off-by: Jaehoon Chung
> ---
> drivers/i2c/s3c24x0_i2c.c | 8
On 11 January 2017 at 08:00, Mario Six wrote:
>
> This patch adds a function to the TPM library, which allows U-Boot to
> flush resources, e.g. keys, from the TPM.
>
> Signed-off-by: Mario Six
> ---
> Changes in v2:
>
> * Added U-Boot command for resource
On 11 January 2017 at 08:01, Mario Six wrote:
> The patch implements secure booting for the mvebu architecture.
>
> This includes:
> - The addition of secure headers and all needed signatures and keys in
> mkimage
> - Commands capable of writing the board's efuses to both
On 8 January 2017 at 22:47, Jaehoon Chung wrote:
> Removes the codes of soft_i2c.
> There is no usasge for universal_c210, also didn't define
> CONFIG_SOFT_I2C_GPIO_SCL.
> This code seems a dead code.
>
> Signed-off-by: Jaehoon Chung
> ---
>
On 9 January 2017 at 01:21, Michal Simek wrote:
> Using enum simplify handling of different bitstream command
> types.
>
> Signed-off-by: Michal Simek
> ---
>
> cmd/fpga.c | 20 +++-
> 1 file changed, 11 insertions(+), 9
On 15 January 2017 at 05:17, Rask Ingemann Lambertsen wrote:
> On Fri, Jan 13, 2017 at 01:29:58AM +, Andre Przywara wrote:
>> Addresses passed on to readl and writel are expected to be of the same
>> size as a pointer. Change the parameter types of sunxi_spi0_read_data()
>>
On Thu, Jan 19, 2017 at 06:57:51AM -0700, Simon Glass wrote:
> On 12 January 2017 at 11:16, Tom Rini wrote:
> > We can make the code read more easily here by simply using memset()
> > always as when we don't have an optimized version of the function we
> > will still have a
On 8 January 2017 at 22:47, Jaehoon Chung wrote:
> Enable the CONFIG_DM_PMIC and CONFIG_DM_PMIC_MAX8998.
> s5pc210_universal board is using max8998 pmic.
> To use the i2c/pmic driver model, enable these configurations.
>
> Signed-off-by: Jaehoon Chung
On 6 January 2017 at 12:09, Andrew F. Davis wrote:
>
> Print statements in SPL depend on lib/common support, so many such
> statements are ifdef'd, move the check to the common.h header and
> remove these inline checks.
>
> Signed-off-by: Andrew F. Davis
> ---
>
On 11 January 2017 at 09:28, Tom Rini wrote:
> On Fri, Jan 06, 2017 at 01:35:45PM -0600, Andrew F. Davis wrote:
>
>> These files are only included for build by the make system
>> when CONFIG_SPL_{EXT,FAT}_SUPPORT is enabled, remove the unneed
>> checks for these in the source
On 12 January 2017 at 11:16, Tom Rini wrote:
> We can make the code read more easily here by simply using memset()
> always as when we don't have an optimized version of the function we
> will still have a version of this function around anyhow.
>
> Cc: Simon Glass
On 12 January 2017 at 11:16, Tom Rini wrote:
> We have long had available optimized versions of the memset and memcpy
> functions that are borrowed from the Linux kernel. We should use these
> in normal conditions as the speed wins in many workflows outweigh the
> relatively
On Sun, Jan 8, 2017 at 8:42 PM, Mark Kettenis wrote:
> The Sinovoip BPI-M2+ is a SBC board based on the H3 SoC. It has 1G of RAM,
> 8G eMMC, a microSD slot, USB, gigabit Ethernet, AP6212 WiFi, HDMI, etc.
Make these list as line-by-line, please.
> ---
>
On the OMAP36xx/37xx the CONTROL_WKUP_CTRL register has
a field (bit 6) named GPIO_IO_PWRDNZ. If 0, the IO buffers which
are related to GPIO_126, 127 and 129 are disabled. Some boards may
need this for MMC. After the PBIAS is configured, this bit should
be set high to enable these GPIO pins.
V3:
On Sun, Jan 15, 2017 at 5:40 PM, Jagan Teki wrote:
> Hi,
>
> I've observed the CMD_ERR in U-Boot while accessing SD with boot from
> eMMC on i.MX6 board.
>
> SPL initializing SD as well eMMC controllers
> a) On SD bootmode: from u-boot prompt mmc dev 0 and mmc dev 1 is
>
On 12/26/2016 06:37 PM, yuantian.t...@nxp.com wrote:
> From: Tang Yuantian
>
> The LS1012A processor has two integrated USB controllers.
> One is USB2.0 controller, the other is USB3.0 controller that
> allow direct connection to the USB ports with appropriate
> protection
From: Jagan Teki
Boot from MMC:
-
U-Boot SPL 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33)
Trying to boot from MMC1
U-Boot 2017.01-rc2-gba3c151-dirty (Jan 02 2017 - 16:59:33 +0100)
CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz)
CPU:
From: Jagan Teki
Add I2C support for Engicam Is.IoT MX6UL module.
isiotmx6ul> i2c bus
Bus 0: i2c@021a
Bus 1: i2c@021a4000
isiotmx6ul> i2c dev 0
Setting bus to 0
isiotmx6ul> i2c dev
Current bus is 0
isiotmx6ul> i2c speed 10
Setting bus speed to 10 Hz
From: Jagan Teki
USDHC base address will assigned by SPL using fsl_esdhc_initialize
and u-boot with devicetree, hence no remove base address assignment
in config files.
Cc: Stefano Babic
Cc: Matteo Lisi
Cc: Michael Trimarchi
From: Jagan Teki
This patch set support Engicam Is.IoT MX6UL board support.
Changes for v2:
- Skiped eMMC node patch
- Rebase to master
Changes for v1:
- Rebase to master
Jagan Teki (9):
configs: imx6: Don't define USDHC2_BASE_ADDR
arm: imx6ul: Add Engicam
Sry
CC:u-boot@lists.denx.de
On 01/19/2017 04:30 PM, Grygorii Strashko wrote:
From: Mugunthan V N
Add support for programmable MAC impedance configuration and
fix typo in DT impedance parameters names.
Signed-off-by: Mugunthan V N
Signed-off-by:
Hi Stefan,
2017-01-19 16:39 GMT+09:00 Stefan Roese :
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index 9ed8da39ef..87cc9439f3 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -287,6 +287,17 @@ config MMC_SDHCI_SPEAR
>
> If unsure, say N.
No comments?
On Sat, Jan 7, 2017 at 12:04 AM, Marty Plummer wrote:
> Greetings,
>
> So, out of a desire to learn (or simply pure masochism), I've taken it
> upon myself to work on mainlining support for a new arm SoC and board,
> which the vendor SDK only provides source
From: Jagan Teki
Add NAND support for Engicam Is.IoT MX6UL board.
Cc: Stefano Babic
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
From: Jagan Teki
Add FEC support for Engicam Is.IoT MX6UL module.
Cc: Stefano Babic
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
From: Jagan Teki
Add config options for booting Linux from NAND in UBI format.
Cc: Stefano Babic
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
From: Jagan Teki
Enable I2C support for Engicam Is.IoT NAND module.
Cc: Stefano Babic
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
From: Jagan Teki
Add FEC node for Engicam Is.IoT MX6UL module.
Cc: Stefano Babic
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
From: Jagan Teki
Add I2C nodes for Engicam Is.IoT MX6UL module.
Cc: Stefano Babic
Cc: Matteo Lisi
Cc: Michael Trimarchi
Signed-off-by: Jagan Teki
---
On 12/12/2016 11:08 PM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Enable DT to support Driver Model.
>
> Signed-off-by: Hou Zhiqiang
> ---
> V5:
> - No change
>
This patch set is applied to fsl-qoriq master, awaiting upstream. Thanks.
York
On 01/16/2017 01:45 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Signed-off-by: Hou Zhiqiang
> ---
> V2:
> - Generate the patch base on the latest code.
>
This set is applied to fsl-qoriq master, awaiting upstream. Thanks.
York
On 12/16/2016 01:29 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> The real size of OCRAM is 128KiB, so correct the size of OCRAM.
> And OCRAM reserved 2MiB space, then add a new macro to describe
> it, which is used for MMU setup.
>
> Signed-off-by: Hou Zhiqiang
On 01/16/2017 05:52 PM, Alison Wang wrote:
> For 64-bit kernel, there is a warning about x1-x3 nonzero in violation
> of boot protocol. To fix this issue, input argument 4 is added for
> armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will
> be set to the right value, such as
Hi Kever and Simon,
Thanks very much for the help. Really appreciate it.
> I didn't see your detail steps for getting u-boot-dtb.bin, does it
> include SPL here?
I'm using this method:
> 2. with "CONFIG_ROCKCHIP_SPL_BACK_TO_BROM", which is default setting
...
> I'm confusing with this
On 01/10/2017 12:57 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
> like LS1043A, LS1046A and LS1012A. But the clocks tree has a
> lot of differences, for instance, the IP modules have different
> dividers to
On Thursday 19 January 2017 09:29 PM, Andrew F. Davis wrote:
> On 01/17/2017 10:14 PM, Lokesh Vutla wrote:
>>
>> [..snip..]
>>
>>> +CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk
>>> am335x-bonegreen am335x-icev2"
>>
>> Just wondering, do we have HS
Hi York,
Sorry for the trouble. I remember I tested it when I submitted the patch.
Anyway, I will check it out.
Regards,
Yuantian
> -Original Message-
> From: york sun
> Sent: Thursday, January 19, 2017 1:20 AM
> To: Y.T. Tang
> Cc: Mingkai Hu
On Thu, Jan 19, 2017 at 05:34:25PM +0100, Jagan Teki wrote:
> On Thu, Jan 19, 2017 at 5:11 PM, Tom Rini wrote:
> > On Thu, Jan 19, 2017 at 04:46:18PM +0100, Jagan Teki wrote:
> >> On Wed, Jan 11, 2017 at 12:14 AM, Tom Rini wrote:
> >> > On Sat, Jan 07,
The check for OMAP3630/3730 only checks for 800MHz 3630/3730, but
anything else is lumped into 36XX/37XX with an assumed 1GHz speed.
Based on the DM3730 TRM bit 9 shows the MPU Frequency (800MHz/1GHZ).
This also adds the ability to distinguish between the DM3730, DM3725,
AM3715, and AM3703 and
On 01/05/2017 08:30 PM, Udit Agarwal wrote:
> Update bootscript and its hdr addresses for Layerscape Chasis 3
> based platforms instead of individual SoCs.
>
> Signed-off-by: Sumit Garg
> Signed-off-by: Udit Agarwal
> ---
>
> Changes for V2:
> Modified
Currently the SPL FIT loader always looks only for the first image in
the /images node a FIT tree, which it loads and later executes.
Generalize this by looking for a "firmware" property in the matched
configuration subnode, or, if that does not exist, for the first string
in the "loadables"
Currently the SPL FIT loader uses the spl_fit_select_fdt() function to
find the offset to the right DTB within the FIT image.
For this it iterates over all subnodes of the /configuration node in
the FIT tree and compares all "description" strings therein using a
board specific matching function.
At the moment we load two images from a FIT image: the actual U-Boot
image and the DTB. Both times we have very similar code to deal with
alignment requirement the media we load from imposes upon us.
Factor out this code into a new function, which we just call twice.
Signed-off-by: Andre Przywara
For a board or platform to support FIT loading in the SPL, it has to
provide a board_fit_config_name_match() routine, which helps to select
one of possibly multiple DTBs contained in a FIT image.
Provide a simple function to cover the two different Pine64 models,
which can be easily told apart by
Hi,
On 01/20/2017 12:37 AM, Jagan Teki wrote:
> On Sun, Jan 15, 2017 at 5:40 PM, Jagan Teki wrote:
>> Hi,
>>
>> I've observed the CMD_ERR in U-Boot while accessing SD with boot from
>> eMMC on i.MX6 board.
>>
>> SPL initializing SD as well eMMC controllers
>> a) On SD
The Pine64 boards require an ARM Trusted Firmware (ATF) image to be
loaded and executes prior to the actual U-Boot proper.
Add a FIT image source file to describe the binaries, also add the
supported DTs to be able to boot multiple boards with one image. Use:
$ tools/mkimage -f
mksunxiboot limits the size of the resulting SPL binaries to pretty
conservative values to cover all SoCs and all boot media (NAND).
In preparation for supporting modern SoCs without NAND, which may
require a really large SPL, introduce comamnd line parameters to
push the possible SPL size to the
The SPL stack is usually located at the end of SRAM A1, where it grows
towards the end of the SPL.
For the really big AArch64 binaries the stack overwrites code pretty
soon, so move the SPL stack to the end of SRAM A2, which is unused at this
time.
Signed-off-by: Andre Przywara
Compiling the SPL in AArch64 results in bigger code, which exceeds the
pretty conservative default limits of mksunxiboot.
Use the newly introduced command line parameters to extend the file size
limit to the actual one, which is 32 KB.
Signed-off-by: Andre Przywara
---
The sunxi-specific SPI load routine only knows how to load a legacy
U-Boot image.
Teach it how to handle FIT images as well, simply by providing the
existing SPL FIT loader with the right loader routine to access the SPI
NOR flash.
Signed-off-by: Andre Przywara
---
The Pine64 (as all 64-bit Allwinner boards so far) need to load an
ARM Trusted Firmware image beside the actual U-Boot proper.
This can now be easily achieved by using the just extended SPL FIT
loading support, so enable it in the Pine64 defconfig.
Signed-off-by: Andre Przywara
Currently the FIT format is not used to its full potential in the SPL:
It only loads the first image from the /images node and appends the
proper FDT.
Some boards and platforms would benefit from loading more images before
starting U-Boot proper, notably Allwinner A64 and ARMv8 Rockchip boards,
So far we were not using the FIT image format to its full potential:
The SPL FIT loader was just loading the first image from the /images
node plus one of the listed DTBs.
Now with the refactored loader code it's easy to load an arbitrary
number of images in addition to the two mentioned above.
As
On 01/04/2017 10:32 AM, York Sun wrote:
> Without a prompt in Kconfig, SECURE_BOOT cannot be selected by
> defconfig. The option was dropped unintentionally when defconfig
> files were cleaned up. Three targets were impacted
> ls1043ardb_SECURE_BOOT, ls2080ardb_SECURE_BOOT,
>
On 12/01/2016 01:20 AM, yuantian.t...@nxp.com wrote:
> From: Tang Yuantian
>
> By default the SATA IP on the ls208Xa SoCs does not generating
> coherent/snoopable transactions. This patch enable it in the
> sata axicc register.
>
> Signed-off-by: Tang Yuantian
Hi Masahiro,
On 20.01.2017 00:16, Masahiro Yamada wrote:
2017-01-19 16:39 GMT+09:00 Stefan Roese :
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 9ed8da39ef..87cc9439f3 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -287,6 +287,17 @@ config
Generally SYSCLK frequency is dependent on on-board switch settings.
It may vary as per requirement, but this doesn't apply to ls1012a.
ls1012a has its SYSCLK frequencies specified in the RM. The fixup
for all 'fixed-clock' compatibles of ls1012a would cause incorrect
SYSCLK frequency values. So
On Mon, Jan 16, 2017 at 02:29:21PM +0100, Jean-Jacques Hiblot wrote:
> Tom, Marek
>
> At the moment, whenever an unaligned address is used in cache
> operations (invalidate_dcache_range, or flush_dcache_range), the
> whole request is discarded for am926ejs. for armV7 or armV8 only
> the aligned
On 11/15/2016 01:33 AM, Minghuan Lian wrote:
> For the function alloc_stream_ids() append_mmu_masters() and
> fdt_fixup_smmu_pcie() there are no related definitions and they
> are never called. So the patch removes the unnecessary declares.
>
> Signed-off-by: Minghuan Lian
On Wed, Jan 11, 2017 at 12:14 AM, Tom Rini wrote:
> On Sat, Jan 07, 2017 at 12:42:34PM +0100, Jagan Teki wrote:
>
>> Cc: Stefano Babic
>> Signed-off-by: Jagan Teki
> [snip]
>> 33 files changed, 21 insertions(+), 12 deletions(-)
> [snip]
Signed-off-by: Sébastien Szymanski
---
cmd/host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/host.c b/cmd/host.c
index 515621b..080b7cf 100644
--- a/cmd/host.c
+++ b/cmd/host.c
@@ -181,7 +181,7 @@ U_BOOT_CMD(
"host ls hostfs
Tom,
The following changes since commit a705ebc81b7f91bbd0ef7c634284208342901149:
Prepare v2017.01 (2017-01-09 11:57:05 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-fsl-qoriq.git
for you to fetch changes up to 5e4a6db8f428cb1f8ced74bc77241144ac0c5b1a:
On 12/25/2016 10:45 PM, Prabhakar Kushwaha wrote:
> Enable UUID and GPT partition support for NXP's ARM based SoCs
> i.e. LS1012A, LS1021A, LS1043A, LS1046A and LS2080A.
>
> Also enable DOS partition for LS1012AFRDM boards.
>
> Signed-off-by: Prabhakar Kushwaha
> ---
On 01/16/2017 06:57 PM, Yangbo Lu wrote:
> Move fdt fixup of 'status' property into a weak function. This allows
> board to define 'status' fdt fixup by themselves.
>
> Signed-off-by: Yangbo Lu
> ---
> Changes for v2:
> - None
> Changes for v3:
> - None
> Changes
On 11/08/2016 10:58 PM, Priyanka Jain wrote:
> It is recommended to set forced-order mode in RNI-6,
> RNI-20 for performance optimization in LS2088A.
>
> Both LS2080A, LS2088A families has CONFIG_LS2080A define.
> As above update is required only for LS2088A, skip this
> for LS2080A SoC family
>
>
On 11/14/2016 07:56 PM, jerry.hu...@nxp.com wrote:
> Enable usb feature for ls1046ardb
>
> Signed-off-by: Changming Huang
> ---
Applied to fsl-qoriq master, awaiting upstream. Thanks.
York
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On 12/09/2016 12:22 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> This patch adds a simple pmic driver for the mc34vr500 pmic which
> is used in conjunction with the fsl T1 and LS1 series SoC.
>
> Signed-off-by: Hou Zhiqiang
> ---
This set is
On 01/17/2017 02:44 AM, Zhiqiang Hou wrote:
> From: Wenbin Song
>
> The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
> alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
> is used to choose which offset will be used.
>
> The LS1043A rev1.0
On Thu, Jan 19, 2017 at 04:46:18PM +0100, Jagan Teki wrote:
> On Wed, Jan 11, 2017 at 12:14 AM, Tom Rini wrote:
> > On Sat, Jan 07, 2017 at 12:42:34PM +0100, Jagan Teki wrote:
> >
> >> Cc: Stefano Babic
> >> Signed-off-by: Jagan Teki
> >
On Thu, Jan 19, 2017 at 5:11 PM, Tom Rini wrote:
> On Thu, Jan 19, 2017 at 04:46:18PM +0100, Jagan Teki wrote:
>> On Wed, Jan 11, 2017 at 12:14 AM, Tom Rini wrote:
>> > On Sat, Jan 07, 2017 at 12:42:34PM +0100, Jagan Teki wrote:
>> >
>> >> Cc: Stefano
On 01/17/2017 10:14 PM, Lokesh Vutla wrote:
>
> [..snip..]
>
>> +CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk
>> am335x-bonegreen am335x-icev2"
>
> Just wondering, do we have HS variants of all these boards? If not we
> can just keep am335x-evm.
>
On 12/06/2016 08:08 PM, Yangbo Lu wrote:
> There would be compiling error as below when enable driver model for esdhc.
> undefined reference to `dm_gpio_get_value'
> undefined reference to `gpio_request_by_name_nodev'
> This patch is to make GPIO support optional with CONFIG_DM_GPIO. Because
> all
On 01/06/2017 01:54 AM, Zhiqiang Hou wrote:
> From: Mingkai Hu
>
> For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
> set. The SMPEN bit should be set before enabling the data cache.
> If not enabled, the cache is not coherent with other cores and
> data
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