On 3.4.2017 16:18, Olliver Schinagl wrote:
> The .read_rom_hwaddr net_ops hook does not check the return value, which
> is why it was never caught that we are currently returning 0 if the
> read_rom_hwaddr function return -ENOSYS and -ENOSYS otherwise.
>
> In this case we can simplify this by
Signed-off-by: Priyanka Jain
Signed-off-by: Suresh Gupta
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig |1 +
arch/arm/dts/fsl-ls2080a-rdb.dts | 22 +++
board/freescale/ls2080ardb/ls2080ardb.c | 23 +++-
Hi,
Marek Vasut writes:
>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>> index b2c7eb1..f58c7ba 100644
>> --- a/drivers/usb/dwc3/core.c
>> +++ b/drivers/usb/dwc3/core.c
>> @@ -125,6 +125,8 @@ static struct dwc3_event_buffer
>>
Hi Simon
Please see my inline reply, thanks a lot!
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: 2017年4月1日 12:22
To: Ken Ma
Cc: U-Boot Mailing List; Stefan Roese; Michal Simek
Subject: [EXT] Re: [PATCH 1/7] scsi: move base, max_lun and
Hi,
Marek Vasut writes:
Merely using dma_alloc_coherent does not ensure that there is no stale
data left in the caches for the allocated DMA buffer (i.e. that the
affected cacheline may still be dirty).
The original code was doing the following (on
Felipe,
> On 05 Apr 2017, at 10:18, Felipe Balbi wrote:
>
>>> Good point on the “long”, especially as I just copied this from other
>>> occurences and it’s consistently wrong throughout DWC3 in U-Boot:
>>
>> Hrm, I thought the driver was ported over from Linux,
Hi Eric,
1. Please use full name in you signature;
2. add commit message for all your commits;
3. add 'rockchip' and module name for all your patches.
4. 'From: ' in not need for patch from yourself.
Thanks,
- Kever
On 04/01/2017 10:42 PM, eric@rock-chips.com wrote:
From: "eric.gao"
Hi
> -Original Message-
> From: Masahiro Yamada [mailto:yamada.masah...@socionext.com]
> Sent: 05 April 2017 06:36
>
> 2017-04-05 14:05 GMT+09:00 Kever Yang :
> > SPL is considered as BL2 in ATF terminology, it needs to load other
> > parts of ATF binary like
Hi Simon
Please see my inline reply, thanks a lot!
Yours,
Ken
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: 2017年4月1日 12:22
To: Ken Ma
Cc: U-Boot Mailing List; Stefan Roese; Michal Simek
Subject: [EXT] Re: [PATCH 3/7] scsi: call
Signed-off-by: Santan Kumar
Signed-off-by: Priyanka Jain
---
arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
Hi Stefan, Hi Simon
Please see my inline reply, thanks!
Yours,
Ken
-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: 2017年4月3日 14:14
To: Simon Glass; Ken Ma
Cc: u-boot@lists.denx.de; Michal Simek; Kostya Porotchkin; Hua Jing; Wilson Ding
Subject: Re: [EXT] Re: [PATCH
Restructure system manager in the preparation to support A10.
No functional change.
Change uint32_t to u32.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile | 5 +-
.../arm/mach-socfpga/include/mach/system_manager.h | 128
Add system manager register struct and macros for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
.../arm/mach-socfpga/include/mach/system_manager.h | 74 +---
.../include/mach/system_manager_arria10.h
Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Kconfig|
Add pinmux support for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/include/mach/pinmux.h | 15 +
arch/arm/mach-socfpga/pinmux_arria10.c
Add config and defconfig for the Arria10 and update socfpga_common.h.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
configs/socfpga_arria10_defconfig | 28 ++
include/configs/socfpga_arria10_socdk.h | 66
On 04/05/2017 04:21 AM, Simon Glass wrote:
> Hi,
>
> On 4 April 2017 at 19:26, Kever Yang wrote:
>> Hi Eddie,
>>
>>
>> We should only need to do only one time cache operation for a buffer
>>
>> ready to do DMA transfer, so you need to remove another cache
Hi,
"Dr. Philipp Tomsich" writes:
Good point on the “long”, especially as I just copied this from other
occurences and it’s consistently wrong throughout DWC3 in U-Boot:
>>>
>>> Hrm, I thought the driver was ported over from Linux, so is this
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
cm_write_with_phase() and
This is the 4th version of patchset to adds support for Intel Arria 10 SoC.
This version mainly resolved comments from Marek and Dinh in [v3]. Only patch
#01,
#14 and #16 have changes in this revision.
This is initial patchset enables the basic support for Arria 10 and other
features will come
Device tree files for Arria 10
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_arria10.dtsi | 859 +
Add compatible strings for Intel Arria 10 SoCFPGA device.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
include/fdtdec.h | 8
lib/fdtdec.c | 8
2 files changed, 16 insertions(+)
diff --git
Add SPL support for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/spl.c | 74 ++---
1 file changed, 69 insertions(+), 5 deletions(-)
diff --git
Hi Jelle,
On Tue, Apr 4, 2017 at 11:59 PM, Jelle van der Waa wrote:
> @@ -22,6 +22,25 @@
> #include
> #include
> #include
> +
You also need
#include
here (in rsa-sign.c as well).
> +#if OPENSSL_VERSION_NUMBER < 0x1010L || defined(LIBRESSL_VERSION_NUMBER)
> +void
Add support for the Arria10 SoCDK.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
board/altera/arria10-socdk/Kconfig | 18 ++
board/altera/arria10-socdk/Makefile | 7 +++
Hi Jelle,
On Tue, Apr 4, 2017 at 11:59 PM, Jelle van der Waa wrote:
> @@ -20,6 +20,19 @@
> #define HAVE_ERR_REMOVE_THREAD_STATE
> #endif
>
> +#if OPENSSL_VERSION_NUMBER < 0x1010L || defined(LIBRESSL_VERSION_NUMBER)
> +void RSA_get0_key(const RSA *r,
> +
Not yet, i rebased against u-boot-net/master. As it is it is a bug however so
we should just put the fix in for now.
On April 5, 2017 8:29:22 AM CEST, Michal Simek wrote:
>On 3.4.2017 16:18, Olliver Schinagl wrote:
>> The .read_rom_hwaddr net_ops hook does not check the
On 4.4.2017 19:53, Joe Hershberger wrote:
> On Mon, Apr 3, 2017 at 9:18 AM, Olliver Schinagl wrote:
>>
>> The .read_rom_hwaddr net_ops hook does not check the return value, which
>> is why it was never caught that we are currently returning 0 if the
>> read_rom_hwaddr function
Hi Tom,
This deals with closing down devices which have used DMA.
he following changes since commit 11db152246607868f0e74db958947fbf79f28119:
Prepare v2017.05-rc1 (2017-04-04 17:53:24 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-dm.git
for you to fetch changes
Restructure misc driver in the preparation to support A10.
Move the Gen5 specific code to gen5 file.
Change all uint32_t_to u32 and check return value from
socfpga_bridges_reset.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile| 2 +-
Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files. Change socfpga_per_reset() return
type to int.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile | 2 +-
Add i2c, timer and other A10 macros.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
Add clock driver support for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile |3 +-
arch/arm/mach-socfpga/clock_manager.c | 10 +
Add reset driver support for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile | 2 +
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 +
Add sdram header file for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 380 +
1 file changed, 380 insertions(+)
create mode 100644
Add misc support for Arria 10.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefile| 1 +
arch/arm/mach-socfpga/include/mach/misc.h | 6 +
arch/arm/mach-socfpga/misc_arria10.c | 258
Update Kconfig and Makefile to enable Arria 10.
Clean up Makefile and sorting *.o alphanumerically.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Kconfig | 10 +
arch/arm/mach-socfpga/Makefile | 46
These registers only available for Gen5 device, exclude them
from Arria 10 build.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
drivers/fpga/socfpga.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
Hi Marek,
On 5 April 2017 at 03:35, Marek Vasut wrote:
> On 04/05/2017 04:21 AM, Simon Glass wrote:
>> Hi,
>>
>> On 4 April 2017 at 19:26, Kever Yang wrote:
>>> Hi Eddie,
>>>
>>>
>>> We should only need to do only one time cache operation for a
2017-04-01 12:22 GMT+08:00 Simon Glass :
> Hi,
>
> On 27 March 2017 at 08:38, wrote:
> > From: Ziping Chen
> >
> > Currently the "led" command only supports the old API without DM.
> >
> > Add DM-based implementation of this
On 04/05/2017 12:08 PM, Simon Glass wrote:
> Hi Marek,
>
> On 5 April 2017 at 03:35, Marek Vasut wrote:
>> On 04/05/2017 04:21 AM, Simon Glass wrote:
>>> Hi,
>>>
>>> On 4 April 2017 at 19:26, Kever Yang wrote:
Hi Eddie,
We should
Hi Stefan,
> On 2017-04-04 01:23, Lukasz Majewski wrote:
> > Hi Stefan,
> >
> >> Hi Lukasz,
> >>
> >> On 2017-04-03 04:20, Lukasz Majewski wrote:
> >> > Hi Stefan,
> >> >
> >> > Thanks for your patch. Please allow me to share some ideas for
> >> > improvements.
> >> >
> >> >> From: Stefan Agner
From: Konstantin Porotchkin
Add NAND to CP master device tree. Add armada-7040-db-nand
device tree for the board configured with NAND boot device.
Add comment about boot device ID to armada-7040-db DTS.
Signed-off-by: Konstantin Porotchkin
Cc: Stefan
On Tue, Apr 4, 2017 at 4:32 PM, Mauricio Cirelli
wrote:
>
> Turing Computer is a designer and manufacturer of ARM-based
> System on Modules, specialized on i.MX SoCs from Freescale/NXP.
> This patch adds support for their Evaluation Board running i.MX6
> Solo, Dual
On 04/05/2017 01:42 PM, Marek Vasut wrote:
> There is no point in having such gargantuan buffer, it only requires
> huge malloc area. Reduce the DFU buffer size.
>
> Signed-off-by: Marek Vasut
Applied all three.
> ---
> include/configs/socfpga_common.h | 2 +-
> 1 file changed,
On 04/05/2017 10:18 AM, Felipe Balbi wrote:
>
> Hi,
>
> Marek Vasut writes:
> Merely using dma_alloc_coherent does not ensure that there is no stale
> data left in the caches for the allocated DMA buffer (i.e. that the
> affected cacheline may still be dirty).
>
On Fri, Mar 31, 2017 at 10:34:35PM -0600, Simon Glass wrote:
> Hi Tom,
>
> On 31 March 2017 at 22:19, Simon Glass wrote:
> > Hi Tom,
> >
> > On 6 February 2017 at 08:32, Simon Glass wrote:
> >>
> >> Hi Tom,
> >>
> >> On 23 January 2017 at 10:22, Tom Rini
Hi Tom,
Please take this PR.
thanks!
Jagan.
The following changes since commit 11db152246607868f0e74db958947fbf79f28119:
Prepare v2017.05-rc1 (2017-04-04 17:53:24 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-sunxi.git master
for you to fetch changes up to
2017-04-01 12:23 GMT+08:00 Simon Glass :
> Hi,
>
> On 27 March 2017 at 08:38, wrote:
> > From: Ziping Chen
> >
> > Sometimes we need to read back the status of a LED.
> >
> > Add a led_get_status function for DM LED support,
On Tue, Mar 28, 2017 at 05:05:09PM +0800, Peng Fan wrote:
> Sync with Linux commit ad0376eb1483b ("Merge tag 'edac_for_4.11_2'").
>
> Signed-off-by: Peng Fan
> Cc: Tom Rini
> ---
> include/linux/math64.h | 172
>
On Wed, Mar 29, 2017 at 12:17:31PM +0100, Andre Przywara wrote:
> Hi,
>
> On 29/03/17 07:57, Maxime Ripard wrote:
> > On Tue, Mar 28, 2017 at 01:45:22AM +0100, Andre Przywara wrote:
> >> The Pine64 (and all other 64-bit Allwinner boards) need to load an
> >> ARM Trusted Firmware image beside the
> On 29/03/17 07:57, Maxime Ripard wrote:
>> On Tue, Mar 28, 2017 at 01:45:22AM +0100, Andre Przywara wrote:
>>> The Pine64 (and all other 64-bit Allwinner boards) need to load an
>>> ARM Trusted Firmware image beside the actual U-Boot proper.
>>> This can now be easily achieved by using the just
On 04/05/2017 11:32 AM, Ley Foon Tan wrote:
> Restructure misc driver in the preparation to support A10.
> Move the Gen5 specific code to gen5 file.
>
> Change all uint32_t_to u32 and check return value from
> socfpga_bridges_reset.
>
> Signed-off-by: Ley Foon Tan
[...]
On 04/05/2017 12:57 PM, Dr. Philipp Tomsich wrote:
>
>> On 05 Apr 2017, at 12:25, Marek Vasut wrote:
>>
>> On 04/04/2017 10:26 PM, Dr. Philipp Tomsich wrote:
>>>
On 04 Apr 2017, at 22:09, Marek Vasut wrote:
> The DWC3 flush expands to a
On 04/05/2017 01:32 PM, Marek Vasut wrote:
> The board is now manufactured by Aries Embedded GmbH , rename it.
>
> Signed-off-by: Marek Vasut
Applied, thanks.
--
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
On 04/05/2017 11:32 AM, Ley Foon Tan wrote:
> Add misc support for Arria 10.
>
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
[...]
> +static int find_peripheral_uart(const void *blob,
> + int child, const char *node_name)
>
On 04/05/2017 11:32 AM, Ley Foon Tan wrote:
> Add compatible strings for Intel Arria 10 SoCFPGA device.
>
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
> ---
Applied.
--
Best regards,
Marek Vasut
Hi Ken,
On 05.04.2017 11:29, Ken Ma wrote:
Hi Stefan, Hi Simon
Please see my inline reply, thanks!
Yours,
Ken
-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: 2017年4月3日 14:14
To: Simon Glass; Ken Ma
Cc: u-boot@lists.denx.de; Michal Simek; Kostya Porotchkin; Hua Jing;
When this board was switched to using more DM drivers we didn't disable
the legacy PCA953X driver. This in turn learn to a build time warning
about implicit functions as i2c.h would not say anything about
'i2c_read' nor 'i2c_write'. But this was not a fatal error as none of
the legacy driver
On 04/05/2017 11:32 AM, Ley Foon Tan wrote:
> Convert Altera DDR SDRAM driver to use Kconfig method.
> Enable ALTERA_SDRAM by default if it is on Gen5 target.
> Arria 10 will have different driver.
>
> Signed-off-by: Tien Fong Chee
> Signed-off-by: Ley Foon Tan
+Tom
Hi Marek,
On 5 April 2017 at 04:21, Marek Vasut wrote:
> On 04/05/2017 12:08 PM, Simon Glass wrote:
>> Hi Marek,
>>
>> On 5 April 2017 at 03:35, Marek Vasut wrote:
>>> On 04/05/2017 04:21 AM, Simon Glass wrote:
Hi,
On 4 April 2017 at 19:26,
From: Konstantin Porotchkin
Add NAND configuration parameters to A8K shared config file.
Add defconfig for db-88f7040 board with boot from NAND setup.
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Igal Liberman
Hi Marek,
On 5 April 2017 at 19:32, Marek Vasut wrote:
> On 04/06/2017 03:24 AM, Simon Glass wrote:
>> Hi Marek,
>>
>> On 5 April 2017 at 15:34, Marek Vasut wrote:
>>> On 04/05/2017 05:03 PM, Simon Glass wrote:
+Tom
Hi Marek,
On 5 April
On Thu, Apr 6, 2017 at 7:37 AM, Peng Fan wrote:
> On Mon, Apr 03, 2017 at 07:23:35PM +0530, Jagan Teki wrote:
>>From: Jagan Teki
>>
>>Since all SabreSD boards support SPL and devicetree
>>update README on respective image name changes
>>while
Enables the pinctrl-single driver to support 16-bit registers. Only
32-bit registers were supported previously. Reduced width registers are
required for some platforms, such as OMAP.
Signed-off-by: James Balean
Cc: Felix Brack
Cc: Simon Glass
On Mon, Apr 03, 2017 at 07:23:35PM +0530, Jagan Teki wrote:
>From: Jagan Teki
>
>Since all SabreSD boards support SPL and devicetree
>update README on respective image name changes
>while loading the SD card.
SPL is not supported by NXP software releases, so I would
On Wed, Apr 5, 2017 at 6:40 PM, Marek Vasut wrote:
> On 04/05/2017 11:32 AM, Ley Foon Tan wrote:
>> Add misc support for Arria 10.
>>
>> Signed-off-by: Tien Fong Chee
>> Signed-off-by: Ley Foon Tan
>
> [...]
>
>> +static int
We should invalidate the dcache before starting the DMA. In case there are
any dirty lines from the DMA buffer in the cache, subsequent cache-line
replacements may corrupt the buffer in memory while the DMA is still going on.
Cache-line replacement can happen if the CPU tries to bring some other
Hi Eric,
On 1 April 2017 at 08:42, wrote:
> From: "eric.gao"
>
> Signed-off-by: eric.gao
> ---
>
> arch/arm/dts/rk3399-evb.dts | 33 ++
> arch/arm/dts/rk3399.dtsi | 72
On 1 April 2017 at 08:42, wrote:
> From: "eric.gao"
>
> Signed-off-by: eric.gao
> ---
>
> configs/evb-rk3399_defconfig| 1 +
> include/configs/rk3399_common.h | 5 -
> 2 files changed, 5 insertions(+), 1
Hi Andy,
On 1 April 2017 at 07:21, Andy Shevchenko
wrote:
> This simple PMU driver allows to tyrn power on and off for selected
> devices. In particularly Intel Tangier needs to power on SDHCI
> controllers in order to access to them during board
Hi Eric,
On 1 April 2017 at 08:42, wrote:
> From: "eric.gao"
>
> After enable log printing to lcd,when the screen start scroll,the
> system crash.And the log is shown as bellow.
>
> "Synchronous Abort" handler, esr 0x9645
> "Synchronous
On Wed, Apr 5, 2017 at 6:39 PM, Marek Vasut wrote:
> On 04/05/2017 11:32 AM, Ley Foon Tan wrote:
>> Restructure misc driver in the preparation to support A10.
>> Move the Gen5 specific code to gen5 file.
>>
>> Change all uint32_t_to u32 and check return value from
>>
Hi York,
On 31 March 2017 at 22:49, york sun wrote:
> On 03/31/2017 09:21 PM, Simon Glass wrote:
>> Hi York,
>>
>> On 23 March 2017 at 20:06, york sun wrote:
>>> Simon,
>>>
>>> I made it work. A patch set will be sent later (much later) after I
>>> clean up
On 1 April 2017 at 00:46, Eddie Cai wrote:
> tinker board support ethernet and usb host, so enable USB, PXE and DHCP
> support.
>
> Signed-off-by: Eddie Cai
> ---
> include/configs/tinker_rk3288.h | 5 -
> 1 file changed, 4
On 1 April 2017 at 08:42, wrote:
> From: "eric.gao"
>
> Signed-off-by: eric.gao
> ---
>
> arch/arm/dts/rk3399-evb.dts | 108
> +++
> configs/evb-rk3399_defconfig | 5 ++
> 2
On Mon, Apr 03, 2017 at 07:23:14PM +0530, Jagan Teki wrote:
>From: Jagan Teki
>
>Add initial dts support for i.MX6 Quad Plus Sabresd board.
>
>Boot from MMC:
>-
>U-Boot SPL 2017.03-33690-ga80e4f6-dirty (Mar 30 2017 - 00:40:29)
>Trying to boot from MMC1
>
Hi Andy,
On 1 April 2017 at 07:11, Andy Shevchenko
wrote:
> On Fri, 2017-03-31 at 22:24 -0600, Simon Glass wrote:
>> Hi Andy,
>>
>> On 20 March 2017 at 06:51, Andy Shevchenko
>> wrote:
>> > On Sun, 2017-03-19 at 20:30 -0600,
Hi Philipp,
On 1 April 2017 at 04:59, Philipp Tomsich
wrote:
> The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
> serial line available via standardised pins on the edge connector and
> available on a RS232 connector).
>
> To support
On 1 April 2017 at 08:42, wrote:
> From: "eric.gao"
>
> if we enable PMIC rk808,the system will halt at very early stage
> ,log is shown as bellow.
>
> INFO:plat_rockchip_pmu_init(1211): pd status 3e
> INFO:BL31: Initializing runtime
Hi Andy,
On 1 April 2017 at 07:21, Andy Shevchenko
wrote:
> From: Felipe Balbi
>
> Intel MID platforms have few microcontrollers inside SoC, one of them
> is so called System Controller Unit (SCU).
>
> Here is the driver to
On 1 April 2017 at 00:49, Eddie Cai wrote:
> Now that most rockchip SoC based board have usb host support, enable
> USB boot targets by default.
>
> Signed-off-by: Eddie Cai
> ---
> include/configs/rockchip-common.h | 1 +
> 1 file changed,
On Thu, Apr 6, 2017 at 7:29 AM, Peng Fan wrote:
> On Mon, Apr 03, 2017 at 07:23:14PM +0530, Jagan Teki wrote:
>>From: Jagan Teki
>>
>>Add initial dts support for i.MX6 Quad Plus Sabresd board.
>>
>>Boot from MMC:
>>-
>>U-Boot SPL
Hi All,
Thank you for your responses. I will submit a new version of the patch
with your suggestions following this.
On 1 April 2017 at 15:22, Simon Glass wrote:
> Can you explain in your commit message why we want this?
Will do. I will be seeking to add TI OMAP device tree
Hi Tom,
On 5 April 2017 at 14:36, Tom Rini wrote:
> On Fri, Mar 31, 2017 at 08:40:26AM -0600, Simon Glass wrote:
>
>> This allows us to use the same DRAM init function on all archs.
>>
>> Signed-off-by: Simon Glass
>> Reviewed-by: Stefan Roese
On 04/05/2017 10:25 PM, Philipp Tomsich wrote:
> Merely using dma_alloc_coherent does not ensure that there is no stale
> data left in the caches for the allocated DMA buffer (i.e. that the
> affected cacheline may still be dirty).
>
> The original code was doing the following (on AArch64, which
On 04/05/2017 05:03 PM, Simon Glass wrote:
> +Tom
>
> Hi Marek,
>
> On 5 April 2017 at 04:21, Marek Vasut wrote:
>> On 04/05/2017 12:08 PM, Simon Glass wrote:
>>> Hi Marek,
>>>
>>> On 5 April 2017 at 03:35, Marek Vasut wrote:
On 04/05/2017 04:21 AM, Simon
On 04/06/2017 04:03 AM, Eddie Cai wrote:
> We should invalidate the dcache before starting the DMA. In case there are
> any dirty lines from the DMA buffer in the cache, subsequent cache-line
> replacements may corrupt the buffer in memory while the DMA is still going on.
> Cache-line replacement
This series addresses some issues when the environment tools
are used as library and linked to an external program.
Stefano Babic (4):
Rename aes.h to uboot_aes.h
env: split fw_env.h in public and private parts
env: add a version number to check API
env: fix memory leak in fw_env
On Wed, Apr 5, 2017 at 11:14 AM, Peter Robinson wrote:
> "On Thu, Mar 30, 2017 at 8:29 PM, Robert Nelson
> wrote:
>> BeagleBone Black Wireless is clone of the BeagleBone Black (BBB) with
>> the Ethernet replaced by a TI wl1835 wireless module.
>>
> -Original Message-
> From: york sun
> Sent: Wednesday, April 5, 2017 9:13 PM
> To: Santan Kumar ; u-boot@lists.denx.de
> Cc: Priyanka Jain
> Subject: Re: [PATCH] armv8: ls2080a: Add serdes2 protocol 0x51 support
>
> On 04/05/2017 02:01 AM,
On 04/05/2017 08:47 AM, Santan Kumar wrote:
>
>>
>> Santan,
>>
>> Does this patch replace another one with subject "armv8: ls2081a: Add
>> serdes2 protocol 0x51 support"? It changes the same file the same way.
>> For future update, you are required to put version number and change log to
>> it.
>>
On 05/04/2017 13:31, Marek Vasut wrote:
> The board is now manufactured by Aries Embedded GmbH , rename it.
>
> Signed-off-by: Marek Vasut
> ---
> arch/arm/Kconfig | 2 +-
> board/{denx => aries}/m28evk/Kconfig | 2 +-
> board/{denx =>
On 05/04/2017 13:31, Marek Vasut wrote:
> The board is now manufactured by Aries Embedded GmbH , rename it.
>
> Signed-off-by: Marek Vasut
> ---
> arch/arm/Kconfig | 2 +-
> board/{denx => aries}/m53evk/Kconfig | 2 +-
> board/{denx =>
Hi Stefan,
On 04/04/2017 20:44, Stefan Agner wrote:
> On 2017-04-04 01:53, Stefano Babic wrote:
>> Hi Stefan,
>>
>> On 03/04/2017 23:02, Stefan Agner wrote:
>>
>>> But then, I don't expect that "/usr/bin/env python" is looking at
>>> PYTHON.
>>>
>>> As far as I understand env, it just looks up
On 05/04/2017 16:46, Tom Rini wrote:
> When this board was switched to using more DM drivers we didn't disable
> the legacy PCA953X driver. This in turn learn to a build time warning
> about implicit functions as i2c.h would not say anything about
> 'i2c_read' nor 'i2c_write'. But this was not a
"On Thu, Mar 30, 2017 at 8:29 PM, Robert Nelson wrote:
> BeagleBone Black Wireless is clone of the BeagleBone Black (BBB) with
> the Ethernet replaced by a TI wl1835 wireless module.
>
> This board can be indentified by the BWAx value after A335BNLT (BBB)
> in the at24
Changes in the environment library are difficult to tracked by programs
using the library. Add simply an API version number that must be
increased each time when the API is changed.
This can be detected and a program can work with different versions of
the library.
Signed-off-by: Stefano Babic
Hi Simon,
On 04/04/2017 08:27 PM, Simon Glass wrote:
> Hi Vikas,
>
> On 4 April 2017 at 15:59, Vikas Manocha wrote:
>> Address translation is not working at present even if SPL_OF_TRANSLATE is
>> enabled which makes this configuration useless. This patch enables address
>>
Not force to use python from PATH. Issue was noted when building with
Yocto, because python from the distro is always taken instead of
python-native built during Yocto process.
Signed-off-by: Stefano Babic
CC: Simon Glass
---
Makefile | 2 +-
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