This is suplement for patch which handle below errata:
A-009007, A-009008, A-008997, A-009798
Signed-off-by: Ran Wang
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 27 ---
2 files changed, 24
Signed-off-by: Ashish Kumar
---
v2:
Add dependent patch set
README| 6 ++
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++
board/freescale/ls1088a/eth_ls1088aqds.c | 7 +++
3 files changed, 20 insertions(+)
diff --git
A Hardware Enablement devroom will be taking place at FOSDEM this year,
on Sunday 10 December 2017. This newly-created devroom is the result of
3 proposals that were merged together. It is co-organized by several
individuals.
The devroom covers all aspects related to hardware enablement and
Orange Pi R1 is a board designed based on Orange Pi Zero, with Wi-Fi
chip replaced and USB Type-A jack replaced with an on-board RTL8152B
USB-Ethernet adapter.
Add support for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/dts/Makefile | 1 +
On 11/13/2017 10:00 AM, Ran Wang wrote:
> Force delay 10ms between each control messages to fix Transcend
> and Kingston DT 101 G2 USB2.0 stick fail to be enumerated by LS208xA.
That means everyone else also suffers this burden, even though it's a
problem specific to LS208x ? What is the real
Thank you Heinrich, I can confirm that current u-boot master works
without reverting 55751ab1. I had problems with u-boot v2017.11-rc2
apparently.
Best regards,
Anton Gerasimov
On 11/11/2017 12:08 PM, Heinrich Schuchardt wrote:
> On 11/10/2017 06:51 PM, Anton Gerasimov wrote:
>> ROM has been
In case of PHY-less mode, there is no interaction with PHY
so auto-neg etc is not required and link will have fixed
attributes
Signed-off-by: Ashish Kumar
Signed-off-by: Prabhakar Kushwaha
---
v2:
Add dependent patch set
Add option to set spi controller clock frequency via device tree
using standard clock bindings.
Define dw_spi_get_clk function as 'weak' as some targets
(like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
and implement dw_spi_get_clk their own way in their clock manager.
Get rid
Force delay 10ms between each control messages to fix Transcend
and Kingston DT 101 G2 USB2.0 stick fail to be enumerated by LS208xA.
Signed-off-by: Ran Wang
---
common/usb.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/common/usb.c b/common/usb.c
index
Implement dw_spi_get_clk function to override its weak
implementation in designware_spi.c driver.
We need this change to get rid of cm_get_spi_controller_clk_hz
function and clock_manager.h include in designware_spi.c driver.
Signed-off-by: Eugeniy Paltsev
---
As discussed with Marek during the LINUX-PITER here is v4 patch:
Add option to set spi controller clock frequency via device tree
using standard clock bindings.
Define dw_spi_get_clk function as 'weak' as some targets
(like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
and
Hi,
On Fri, Nov 10, 2017 at 10:21:10PM +0530, Jagan Teki wrote:
> Add verified-boot documentation for sunxi a64 platform.
>
> Signed-off-by: Jagan Teki
> ---
> Changes for v2:
> - New patch
>
> board/sunxi/README.sunxi64 | 177
>
Hi,
On Fri, Nov 10, 2017 at 10:21:08PM +0530, Jagan Teki wrote:
> Enable FIT_SIGNATURE for sunxi a64.
>
> Signed-off-by: Jagan Teki
> ---
> Changes for v2:
> - Use imply instead of select
>
> arch/arm/mach-sunxi/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
>
Hi Marek,
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Monday, November 13, 2017 5:34 PM
> To: Ran Wang ; Bin Meng ;
> Heiko Schocher
> Cc: u-boot@lists.denx.de
> Subject: Re: [PATCH] usb: Add delay to fix
When building on a multi-core machine for an SPL-enabled board that
also uses CONFIG_OF_EMBED, the following error can be encountered
due to a race condition:
make[3]: *** No rule to make target 'spl/dts/dt.dtb.o', needed by
'spl/dts/built-in.o'. Stop.
../scripts/Makefile.spl:364: recipe
Allow SPL to access binman symbols and use this to get the address of
U-Boot. This falls back to CONFIG_SYS_TEXT_BASE if the binman symbol
is not available.
Signed-off-by: Simon Glass
---
common/spl/spl.c | 16 ++--
include/spl.h| 11 +++
2 files
For testing we need to build some ELF files containing binman symbols. Add
these to the Makefile and check in the binaries:
u_boot_binman_syms - normal, valid ELF file
u_boot_binman_syms_bad - missing the __image_copy_start symbol
u_boot_binman_syms_size - has a binman symbol with an
This file contains the SPL device tree. Add support for including this by
itself in images.
Signed-off-by: Simon Glass
---
tools/binman/etype/u_boot_spl_dtb.py| 17 +
tools/binman/ftest.py | 7 +++
The elf module can provide some debugging information to assist with
figuring out what is going wrong. This is also useful in tests. Update the
-D option so that it is passed through to tests as well.
Signed-off-by: Simon Glass
---
tools/binman/binman.py | 6 --
This area of the image contains symbols whose values are filled in by
binman. If this feature is not used, the table is empty.
Add this to the ARM SPL link script.
Signed-off-by: Simon Glass
---
arch/arm/config.mk | 6 --
arch/arm/cpu/u-boot-spl.lds | 7 +++
> -Original Message-
> From: York Sun
> Sent: Monday, November 13, 2017 10:33 PM
> To: Rajesh Bhagat ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Priyanka Jain
> ; Ashish Kumar
>
> -Original Message-
> From: York Sun
> Sent: Monday, November 13, 2017 10:33 PM
> To: Rajesh Bhagat ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Priyanka Jain
>
> Subject: Re: [PATCH v5 0/7] Add VID support
In some cases we need to read symbols from U-Boot. At present we have a
a few cases which does this via 'nm' and 'grep'.
It is better to use objdump since that tells us the size of the symbols
and also whether it is weak or not.
Add a new module which reads ELF information from files. Update
Binman construct images consisting of multiple binary files. These files
sometimes need to know (at run timme) where their peers are located. For
example, SPL may want to know where U-Boot is located in the image, so
that it can jump to U-Boot correctly on boot.
This series implements this,
This file contains SPL image without a device tree. Add support for
including this in images.
Signed-off-by: Simon Glass
---
tools/binman/etype/u_boot_spl_nodtb.py| 17 +
tools/binman/ftest.py | 5 +
This feature is now supported. Drop the incorrect comment.
Signed-off-by: Simon Glass
---
tools/binman/ftest.py | 1 -
1 file changed, 1 deletion(-)
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index ed0697af006..590299da8bc 100644
--- a/tools/binman/ftest.py
Hey all,
I've released v2017.11 and it's now live on git and FTP and ACD (along
with PGP sig file).
We've had another good all-around release, and I like it.
The current schedule is that v2018.01-rc1 will be tagged on December
4th, with -rc2 on the 18th, -rc3 on January 1st and the release on
This is only 3 bytes long which is not enough to hold two symbol values,
needed to test the binman symbols feature. Increase it to 15 bytes.
Using very small regions is useful since we can easily compare them in
tests and errors are fairly easy to diagnose.
Signed-off-by: Simon Glass
Update tegra to use binman for image creation. This still includes the
current Makefile logic, but a later patch will remove this. Three output
files are created, all of which combine
SPL and U-Boot:
u-boot-tegra.bin - standard image
u-boot-dtb-tegra.bin - same as u-boot-tegra.bin
Add this feature to the README.
Signed-off-by: Simon Glass
---
tools/binman/README | 32 +++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/tools/binman/README b/tools/binman/README
index 4ef76c8f089..08c3e56bdef 100644
---
Hi Patrice,
> -Original Message-
> From: Patrice CHOTARD
> Sent: Monday, November 13, 2017 8:26 AM
> To: u-boot@lists.denx.de; albert.u.b...@aribaud.net; s...@chromium.org; Vikas
> MANOCHA
> Cc: Patrice CHOTARD ; Patrick DELAUNAY
>
Binman construct images consisting of multiple binary files. These files
sometimes need to know (at run timme) where their peers are located. For
example, SPL may want to know where U-Boot is located in the image, so
that it can jump to U-Boot correctly on boot.
In general the positions where the
SPL supports reading U-Boot from a RAM location. At present this is
hard-coded to the U-Boot text base address. Use binman to allow this to
come from the image file, if binman is used.
Signed-off-by: Simon Glass
---
common/spl/spl_ram.c | 19 +++
1 file
Restructures common driver to support LTC3882 voltage regulator
chip.
Signed-off-by: Ashish Kumar
Signed-off-by: Rajesh Bhagat
---
Changes in v6:
None
Changes in v5:
None
Changes
Adds a board specific API namely board_adjust_vdd which
is required to define the board VDD adjust settings.
Signed-off-by: Ashish Kumar
Signed-off-by: Rajesh Bhagat
---
Changes in v6:
Moves IR chip (IR36021) specific code in flag to resolve
compilation issue where it is not present. For example,
LS1088A is having a new LTC3882 voltage chip.
Signed-off-by: Ashish Kumar
Signed-off-by: Rajesh Bhagat
---
Changes in v6:
Hi,
On 13.11.2017 16:27, Gerald Van Baren wrote:
> Hi Michal, Mike,
>
> On Mon, Nov 13, 2017 at 9:48 AM, Michal Simek
> wrote:
>> On 13.11.2017 15:35, Mike Looijmans wrote:
>>> On 10-11-17 11:58, Michal Simek wrote:
Hi,
this series is trying to cleanup
Adds below LTC3882 voltage regulator config:
CONFIG_VOL_MONITOR_LTC3882_READ
CONFIG_VOL_MONITOR_LTC3882_SET
Signed-off-by: Ashish Kumar
Signed-off-by: Rajesh Bhagat
---
Changes in v6:
This patch adds the support for VID on LS1088AQDS and LS1088ARDB systems.
It reads the fusesr register and changes the VDD accordingly by adjusting
the voltage via LTC3882 regulator.
This patch also takes care of the special case of 0.9V VDD is present in
fusesr register. In that case,it also
Adds LTC3882 voltage regulator chip support in common VID driver.
And adds VID support for LS1088A QDS and RDB platforms.
Rajesh Bhagat (7):
armv8: lsch3: Add serdes and DDR voltage setup
board: common:vid: Add LS1088A VID Supported voltage values
board: common: vid: Add board specific vdd
Adds below voltage values supported by LS1088A Soc:
1.025 V(default), 0.9875V, 0.9750 V, 0.9V, 1.0 V, 1.0125 V, 1.0250 V
Signed-off-by: Ashish Kumar
Signed-off-by: Rajesh Bhagat
---
Changes in v6:
None
Changes in v5:
None
Changes in v4:
Adds SERDES voltage and reset SERDES lanes API and makes
enable/disable DDR controller support 0.9V API common.
Signed-off-by: Ashish Kumar
Signed-off-by: Rajesh Bhagat
---
Changes in v6:
Dear Tom,
In message <20171114011747.GH27034@bill-the-cat> you wrote:
>
> I've released v2017.11 and it's now live on git and FTP and ACD (along
> with PGP sig file).
Thanks, and the release statistics are also available now, see [1]
Here the short version:
Changes since v2017.09:
Processed
> -Original Message-
> From: Rajesh Bhagat
> Sent: Tuesday, November 14, 2017 9:18 AM
> To: York Sun ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Priyanka Jain
> ; Ashish Kumar
> Subject: RE:
I'm trying to us a 1g micron spi flash in uboot, but it shares the same
jedec id as n25q512a.
In drivers/mtd/spi/spi_flash_ids.c the mt25qu01g is not defined.
Has anyone encountered this issue?
What can I do to resolve it?
Scott
___
U-Boot mailing list
Hi!
Interesting stuff.
I could be wrong but from my understanding the devroom is scheduled for Sunday
4th of February 2018, during FOSDEM, NOT on the 10th of December 2017...
Please clarify that, thank you!
Cheers,
Fil
On 13 November 2017 11:57:31 CET, Paul Kocialkowski
On 10-11-17 11:58, Michal Simek wrote:
Hi,
this series is trying to cleanup ps7_init* file that we don't need to
have the same copy of the same functions in different locations.
This work is done based on solution from Topic.nl for miami boards
where format was changed a little bit to save one
Hi,
Le lundi 13 novembre 2017 à 11:57 +0100, Paul Kocialkowski a écrit :
> A Hardware Enablement devroom will be taking place at FOSDEM this
> year, on Sunday 10 December 2017. This newly-created devroom is the
> result of 3 proposals that were merged together. It is co-organized by
> several
On 13.11.2017 15:35, Mike Looijmans wrote:
> On 10-11-17 11:58, Michal Simek wrote:
>> Hi,
>>
>> this series is trying to cleanup ps7_init* file that we don't need to
>> have the same copy of the same functions in different locations.
>> This work is done based on solution from Topic.nl for miami
在 2017-11-13 20:38,Maxime Ripard 写道:
Hi,
On Mon, Nov 13, 2017 at 07:34:46PM +0800, Icenowy Zheng wrote:
+++ b/configs/orangepi_r1_defconfig
@@ -0,0 +1,19 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=624
+CONFIG_DRAM_ZQ=3881979
+CONFIG_DRAM_ODT_EN=y
+#
Hi,
On Mon, Nov 13, 2017 at 07:34:46PM +0800, Icenowy Zheng wrote:
> +++ b/configs/orangepi_r1_defconfig
> @@ -0,0 +1,19 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_SUNXI=y
> +CONFIG_MACH_SUN8I_H3=y
> +CONFIG_DRAM_CLK=624
> +CONFIG_DRAM_ZQ=3881979
> +CONFIG_DRAM_ODT_EN=y
> +# CONFIG_VIDEO_DE2 is not set
>
Hello Nobuhiro
On Sunday, November 12, 2017, Nobuhiro Iwamatsu wrote:
> >> Maybe we can compromise on everything in mach-renesas??
> >
> > OK, I can go with mach-renesas, thanks again!
>
> +1
>
> Chirs,:
> The reason we are using mach-rmobile is that the code merged first was
> rmobile SoC.
>
On 11/06/2017 02:16 PM, Jorge Ramirez-Ortiz wrote:
Save the environment data at the end of the boot partition on emmc
any progress on this patchset?
the db410c emmc support remains broken on the dragonboard 410c.
TIA
Jorge
___
U-Boot mailing list
On 11/13/2017 10:43 AM, Ran Wang wrote:
> Hi Marek,
>
>> -Original Message-
>> From: Marek Vasut [mailto:ma...@denx.de]
>> Sent: Monday, November 13, 2017 5:34 PM
>> To: Ran Wang ; Bin Meng ;
>> Heiko Schocher
>> Cc:
Dear Prabhakar,
In message
you wrote:
>
> Why ROM MAC address getting overwritten by environment env MAC address.
Because in U-Boot we give the user the freedom to do what he
needs/wants to do. Usually the
Dear Heinrich,
In message <20171110204634.20515-1-xypron.g...@gmx.de> you wrote:
> 0 is not a pointer. So do not compare pointers to 0.
Who says so? 0 can be the value of a pointer to a valid, existing
address. For example a large number of Power Architecture systems
map the RAM beginning at
Dear necib yassine,
In message
you wrote:
>
> Is there any way to set up a security (for instance password...) either any
> users cannot handle u-boot environments variables ?
Re password: you want to read doc/README.autoboot,
On Mon, Nov 13, 2017 at 11:53:35AM +0530, Faiz Abbas wrote:
> Hi
>
> On Monday 23 October 2017 01:28 PM, Faiz Abbas wrote:
> > The dra7xx series of SOCs contain a temperature sensor and an
> > associated analog-to-digital converter (ADC) which produces
> > an output which is proportional to the
Hi Michal, Mike,
On Mon, Nov 13, 2017 at 9:48 AM, Michal Simek
wrote:
> On 13.11.2017 15:35, Mike Looijmans wrote:
>> On 10-11-17 11:58, Michal Simek wrote:
>>> Hi,
>>>
>>> this series is trying to cleanup ps7_init* file that we don't need to
>>> have the same copy of
On 11/12/2017 09:29 PM, Rajesh Bhagat wrote:
> Adds LTC3882 voltage regulator chip support in common VID driver.
> And adds VID support for LS1088A QDS and RDB platforms.
>
> Rajesh Bhagat (7):
> armv8: lsch3: Add serdes and DDR voltage setup
> board: common:vid: Add LS1088A VID Supported
When I use ATF tools from armada-17.08 release everything builds and
boots fine. armaba-17.10 seems to be broken(?)
12.11.2017 14:07, Matwey V. Kornilov пишет:
>
> SATA image from here:
>
> http://wiki.espressobin.net/tiki-index.php?page=Boot+ESPRESSObin+from+SATA+drive
>
> doesn't even print
On 11/13/2017 10:47 AM, Eugeniy Paltsev wrote:
> Add option to set spi controller clock frequency via device tree
> using standard clock bindings.
>
> Define dw_spi_get_clk function as 'weak' as some targets
> (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) fon't use standard clock API
On 11/12/2017 09:30 PM, Rajesh Bhagat wrote:
> Adds SERDES voltage and reset SERDES lanes API and makes
> enable/disable DDR controller support 0.9V API common.
>
> Signed-off-by: Ashish Kumar
> Signed-off-by: Rajesh Bhagat
> ---
> Changes in v5:
From: Patrice Chotard
The SDRAM region was setup with the wrong attributes.
It must be set to :
_ XN_EN (Execution of an instruction fetched from this region permitted)
_ O_I_WB_RD_WR_ALLOC (Outer and inner write-back, write and read allocate)
This fixes hard fault
On 11/13/2017 10:47 AM, Eugeniy Paltsev wrote:
> Implement dw_spi_get_clk function to override its weak
> implementation in designware_spi.c driver.
>
> We need this change to get rid of cm_get_spi_controller_clk_hz
> function and clock_manager.h include in designware_spi.c driver.
>
>
Since RZ/A1 (R7S72100) does not support HS mode, remove it from the
host caps.
Signed-off-by: Chris Brandt
---
drivers/mmc/sh_mmcif.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c
index 1ff59f06d5..4b62795044
On Mon, Nov 13, 2017 at 09:04:40PM +0100, Wolfgang Denk wrote:
> Dear Heinrich,
>
> In message <20171110204634.20515-1-xypron.g...@gmx.de> you wrote:
> > 0 is not a pointer. So do not compare pointers to 0.
>
> Who says so? 0 can be the value of a pointer to a valid, existing
> address. For
Some controllers have a 32-bit data buffer register and do not allow
any other access besides 32-bit read/write.
Signed-off-by: Chris Brandt
---
arch/arm/mach-rmobile/include/mach/sh_sdhi.h | 1 +
drivers/mmc/sh_sdhi.c| 21 -
While the USB HW in the RZ/A is basically the same, there are some
differences from the original versions that were in the SH4 SoCs.
Signed-off-by: Chris Brandt
---
drivers/usb/host/r8a66597-hcd.c | 46 +
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