Hi Pali,
Follow up on the topic of slow/fast SPL SPI loading.
common/spl/spl_spi.c
/*
* Load U-Boot image from SPI flash into RAM
* In DM mode: defaults speed and mode will be
* taken from DT when available
*/
flash = spi_flash_probe(sf_bus,
Hi Martin
On Wed, Aug 3, 2022 at 9:55 PM Martin Bonner wrote:
>
> The only changes from [PATCH v2] are
> 1. It is (I think) a valid patch file
> 2. It has come from my corporate email address (which surprisingly forces
> less mangling than gmail).
> 3. I have extended the commit message
On 8/4/22 09:24, Martin Bonner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On Wed, 3 Aug 2022 at 19:14, Simon Glass wrote:
>
>> Hi Martin,
>>
>> On Wed, 3 Aug 2022 at 04:05, Martin Bonner
>> wrote:
>>>
>>> I and my colleagues have
On Thu, 2022-08-04 at 11:02 +0200, Marek Vasut wrote:
> On 8/4/22 10:15, Philip Oberfichtner wrote:
> > Before this commit, the SPL could enable the PL310 L2 cache [1],
> > but the
> > cache maintenance functions from cache-pl310.c were only useable
> > for
> > non-SPL builds.
> >
> > After
Hi Pali,
On Wed, Aug 3, 2022 at 3:24 AM Pali Rohár wrote:
>
> On Tuesday 02 August 2022 15:13:13 Tony Dinh wrote:
> > Hi Pali,
> >
> > On Tue, Aug 2, 2022 at 3:00 PM Pali Rohár wrote:
> > >
> > > Hello! We have tested that A385 BootROM on Turris Omnia board is much
> > > slower when reading
On 8/3/22 20:14, Simon Glass wrote:
Hi Heinrich,
On Tue, 2 Aug 2022 at 10:22, Heinrich Schuchardt
wrote:
On 8/2/22 14:41, Simon Glass wrote:
Hi Heinrich,
On Tue, 2 Aug 2022 at 03:50, Heinrich Schuchardt
wrote:
Both the 'host' and the 'efiloader' block devices use the same parent
Hi Ilias, Akashi-san,
On Wed, 27 Jul 2022 at 10:56, Takahiro Akashi
wrote:
>
> On Wed, Jul 27, 2022 at 10:08:00AM +0900, Takahiro Akashi wrote:
> > On Fri, Jul 22, 2022 at 11:45:49AM +0300, Ilias Apalodimas wrote:
> > > Hi Kojima-san,
> > >
> > > On Fri, 22 Jul 2022 at 05:36, Masahisa Kojima
> >
This series makes changes to use the DM gpio APIs so that KIRKWOOD_GPIO
can be disabled on these boards.
Chris Packham (6):
ARM: kirkwood: SBx81LIFKW: remove direct access of GPIO registers
ARM: kirkwood: SBx81LIFKW: update for DM_GPIO
ARM: kirkwood: SBx81LIFKW: enable CMD_GPIO
ARM:
DM_GPIO was already enabled so the MVEBU_GPIO was already available.
Having updated the board code to use the DM_GPIO APIs the KIRKWOOD_GPIO
driver became unnecessary. Disable it for SBx81LIFKW.
Signed-off-by: Chris Packham
---
configs/SBx81LIFKW_defconfig | 1 -
1 file changed, 1 deletion(-)
Update mv88e61xx_hw_reset() to use the DM_GPIO API to toggle the reset
line for the linkstreet switch.
Signed-off-by: Chris Packham
---
board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git
Replace code that accessed the GPIO registers directly with code that
makes use of the LED_GPIO driver.
Signed-off-by: Chris Packham
---
arch/arm/dts/kirkwood-atl-sbx81lifkw.dts| 14 ++
board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c | 50 +
configs/SBx81LIFKW_defconfig
For debugging it is convenient to query/access GPIOs from the command
line.
Signed-off-by: Chris Packham
---
configs/SBx81LIFKW_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig
index 90800e2dd3ee..ad7e2e976d2a 100644
---
On Wed, 3 Aug 2022 at 19:14, Simon Glass wrote:
> Hi Martin,
>
> On Wed, 3 Aug 2022 at 04:05, Martin Bonner
> wrote:
> >
> > I and my colleagues have a number of patches we would like to
> > contribute back to the community, however for various reasons
> > (principally operating inside
Hi,
The current users of kw_gpio.c should be able to switch to
mvebu_gpio.c with some minor changes (the equivalent linux driver
supports the kirkwood Soc). I'll try and take a look and convert my
boards over. I could do a blind conversion of the other boards if
no-one with actual hardware
When booting a fresh board having a random Ethernet address enables
using the network device to program the board.
Signed-off-by: Chris Packham
---
configs/SBx81LIFKW_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig
index
DM_GPIO was already enabled so the MVEBU_GPIO was already available.
Disable KIRKWOOD_GPIO as it was unnecessary.
Signed-off-by: Chris Packham
---
configs/SBx81LIFXCAT_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig
> Signed-off-by: Martin Bonner
Does it matter that v3 is signed off by martingreybe...@gmail.com but emailed
by martin.bon...@entrust.com?
*I* know that they are the same person, but you only have my word for that.
(OTOH, you can compare this patch to v2 and see they are the same.)
--
Hi
On Thu, Aug 4, 2022 at 8:29 AM Martin Bonner wrote:
>
> > Signed-off-by: Martin Bonner
>
> Does it matter that v3 is signed off by martingreybe...@gmail.com but emailed
> by martin.bon...@entrust.com?
>
> *I* know that they are the same person, but you only have my word for that.
> (OTOH,
Hi Simon,
Am 03.08.2022 um 20:14 schrieb Simon Glass:
Hi Stefan,
On Tue, 2 Aug 2022 at 07:45, Stefan Herbrechtsmeier
wrote:
Hi Simon,
Am 02.08.2022 um 14:41 schrieb Simon Glass:
Hi Stefan,
On Tue, 2 Aug 2022 at 06:29, Stefan Herbrechtsmeier
wrote:
From: Stefan Herbrechtsmeier
Remove
On Thursday 04 August 2022 11:43:57 Chris Packham wrote:
> The last user of this driver was removed in commit dee08b1999e2 ("arm:
> Remove gplugd board"). Remove the unused driver.
>
> Signed-off-by: Chris Packham
Acked-by: Pali Rohár
> ---
>
> drivers/gpio/Makefile | 1 -
>
On 8/4/22 10:15, Philip Oberfichtner wrote:
Before this commit, the SPL could enable the PL310 L2 cache [1], but the
cache maintenance functions from cache-pl310.c were only useable for
non-SPL builds.
After enabling the cache one must be able to flush it, too. Thus this
commit allows
Before this commit, the SPL could enable the PL310 L2 cache [1], but the
cache maintenance functions from cache-pl310.c were only useable for
non-SPL builds.
After enabling the cache one must be able to flush it, too. Thus this
commit allows cache-pl310.c to be included in the SPL build.
[1] See
From: Marek Vasut
Enable d-cache early in SPL right after DRAM is started up.
This reduces U-Boot proper load time by 650ms when loaded
from SPI NOR.
Signed-off-by: Marek Vasut
Signed-off-by: Philip Oberfichtner
---
board/dhelectronics/dh_imx6/dh_imx6_spl.c | 27 +++
1
Hi Weijie,
happy to see this series posted!
Trying to apply it unfortunately fails due to errornous line-breaks,
supposedly inserted by your MUA, see below.
I didn't go beyond the first patch and it'd be nice if you report the
whole series without the wrong line-breaks.
Cheers
Daniel
On
Hi Daniel,
Thanks for the reminder.
I found more errornous line-breaks in other patches...
I'll find a way to fix that.
Best Regards,
Weijie
On Thu, 2022-08-04 at 10:37 +0200, Daniel Golle wrote:
> Hi Weijie,
>
> happy to see this series posted!
> Trying to apply it unfortunately fails due to
On 8/4/22 10:15, Philip Oberfichtner wrote:
From: Marek Vasut
Enable d-cache early in SPL right after DRAM is started up.
This reduces U-Boot proper load time by 650ms when loaded
from SPI NOR.
Signed-off-by: Marek Vasut
Signed-off-by: Philip Oberfichtner
---
All 3 MPP pins (20, 21 and 22) can be configured individually and also can
be configured to GPIO functions. Fix definitions for these MPP pins in
existing pin groups. After this change GPIO function can be enabled just
for one of these 3 pins.
Signed-off-by: Pali Rohár
---
In more cases group name consist of function name followed by function
number. So if function name is just prefix of group name, show group name.
So in 'pinmux status -a' command output would be visible also extended
function number, which is useful for debugging.
Signed-off-by: Pali Rohár
---
Before this commit, the SPL could enable the PL310 L2 cache [1], but the
cache maintenance functions from cache-pl310.c were only useable for
non-SPL builds.
After enabling the cache one must be able to flush it, too. Thus this
commit allows cache-pl310.c to be included in the SPL build.
[1] See
From: Marek Vasut
Enable d-cache early in SPL right after DRAM is started up.
This reduces U-Boot proper load time by 650ms when loaded
from SPI NOR.
Signed-off-by: Marek Vasut
Signed-off-by: Philip Oberfichtner
---
Changes in v2:
- Add comment to explain the relevance of
The device ignores any levels or transitions on the SCL pin when the device
is idle, asleep or during waking up.
Linux kernel driver for atsha204a (atmel-sha204a.ko) also ignores return
value from i2c wakeup send command, see:
On 16/05/2022 02.26, Ramon Fried wrote:
> On Wed, May 11, 2022 at 5:13 PM Rasmus Villemoes
> wrote:
>>
>> Not only does eqos_remove() fail to free the buffers that have been
>> allocated by eqos_probe_resources_core(), it repeats those allocations
>> and thus drops twice as much memory on the
On Thu, Aug 04, 2022 at 12:56:45PM +0200, Philip Oberfichtner wrote:
> Before this commit, the SPL could enable the PL310 L2 cache [1], but the
> cache maintenance functions from cache-pl310.c were only useable for
> non-SPL builds.
>
> After enabling the cache one must be able to flush it, too.
On 8/4/22 11:19, Philip Oberfichtner wrote:
[...]
@@ -46,6 +45,7 @@ else
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
endif
+obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
Doesn't this need SPL/TPL Kconfig symbols and
On 16/05/2022 02.27, Ramon Fried wrote:
> On Wed, May 11, 2022 at 5:58 PM Rasmus Villemoes
> wrote:
>>
>> I have an iMX8MP with a ti,dp83867 phy in front of the eqos
>> interface. The phy is Gbit capable - however, the C and D differential
>> pairs are not physically routed to the RJ45 connector.
Thanks.
Reviewed-by: Billy Tsai
On 2022/8/4, 9:02 AM, "Dhananjay Phadke" wrote:
Ported as is, makes it easier to add readable GPIO definitions
in DTS files.
Signed-off-by: Dhananjay Phadke
---
include/dt-bindings/gpio/aspeed-gpio.h | 49 ++
This addition allows UEFI applications running under u-boot to access
peripherals on SPI busses. It is based on the UEFI Platform
Initialization (PI) Specification, Version 1.7 Errata A (April 2020).
Only the core functionality required to discover SPI peripherals and
communicate with them is
Signed-off-by: Paul Barker
---
configs/am335x_evm_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index b500ed0fdd8d..4984d66dc1ce 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -92,6 +92,7
These patches add support for the UEFI SPI I/O protocol defined in the
UEFI Platform Initialization (PI) Specification, Version 1.7 Errata A
(April 2020). This allows a UEFI application to interact with devices
on the SPI bus.
The code here is self-contained and easy to enable/disable at compile
Add properties to the Authenta SPI flash device node to enable access by
a UEFI application using a fixed GUID. Also specify that this device is
JEDEC compatible so that it is correctly initialized when running
`sf probe`.
Signed-off-by: Paul Barker
---
arch/arm/dts/am335x-sancloud-bbe-lite.dts
Macro PIN_GRP() is not used, remove it.
Signed-off-by: Pali Rohár
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index
On 12/05/2022 09.33, Rasmus Villemoes wrote:
> I need the dwc_eth_qos to gain a fix similar to what fec_mxc got in
> 89b5bd54c1a4.
>
> The first patch provides a simplification around the logic for
> fetching the phy's address, so there's one less case to worry about.
>
> The second introduces a
Makes it easier to add readable GPIO definitions in DTS files
for Aspeed SOC based boards.
Ported with small edits to add IBM copyright statement and fix
for checkpatch warning.
Signed-off-by: Dhananjay Phadke
Reviewed-by: Billy Tsai
Acked-by: Chia-Wei Wang
---
On 8/3/2022 7:35 PM, Joel Stanley wrote:
On Thu, 4 Aug 2022 at 01:02, Dhananjay Phadke
wrote:
Ported as is, makes it easier to add readable GPIO definitions
in DTS files.
Signed-off-by: Dhananjay Phadke
---
include/dt-bindings/gpio/aspeed-gpio.h | 49 ++
1 file
On Wed, 3 Aug 2022 at 21:37, Weijie Gao wrote:
>
> This patch adds watchdog support for MediaTek MT7986 SoC
>
> Signed-off-by: Weijie Gao
> ---
> drivers/watchdog/mtk_wdt.c | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Simon Glass
On Wed, 3 Aug 2022 at 21:37, Weijie Gao wrote:
>
> This patch add general-purpose timer support for MediaTek MT7981/MT7986.
> These two SoCs uses a newer version of timer with its register definition
> slightly changed.
>
> Signed-off-by: Weijie Gao
> ---
> drivers/timer/mtk_timer.c | 59
On Wed, 3 Aug 2022 at 21:35, Weijie Gao wrote:
>
> This patch adds general board files based on MT7986 SoCs.
>
> The SD/eMMC controller on MT7986A and MT7986B have different pin
> configurations so that four different reference board configs has to be
> added.
>
> Signed-off-by: Weijie Gao
> ---
Hi Weijie,
On Wed, 3 Aug 2022 at 21:35, Weijie Gao wrote:
>
> This patch adds basic support for MediaTek MT7981 SoC.
> This include the file that will initialize the SoC after boot and its
> device tree.
>
> Signed-off-by: Weijie Gao
> ---
> arch/arm/dts/mt7981.dtsi | 288
On Wed, 3 Aug 2022 at 21:37, Weijie Gao wrote:
>
> This patch adds PWM support for MediaTek MT7981 SoC.
> MT7981 uses a different register offset so we have to add a version field
> to indicate the IP core version.
>
> Signed-off-by: Weijie Gao
> ---
> drivers/pwm/pwm-mtk.c | 34
On Wed, 3 Aug 2022 at 21:37, Weijie Gao wrote:
>
> This patch adds PWM support for MediaTek MT7986 SoC.
>
> Signed-off-by: Weijie Gao
> ---
> drivers/pwm/pwm-mtk.c | 6 ++
> 1 file changed, 6 insertions(+)
Reviewed-by: Simon Glass
On Wed, 3 Aug 2022 at 21:39, Weijie Gao wrote:
>
> This patch adds support for a clock node to configure its parent clock
> where possible.
>
> Signed-off-by: Weijie Gao
> ---
> drivers/clk/mediatek/clk-mtk.c | 79 --
> drivers/clk/mediatek/clk-mtk.h | 2 +
> 2
On Wed, 3 Aug 2022 at 21:37, Weijie Gao wrote:
>
> The input clock for uart is too slow (25MHz) which introduces frequent data
> error on both receiving and transmitting even if the baudrate is 115200.
>
> Using high-speed can significantly solve this issue.
>
> Signed-off-by: Weijie Gao
> ---
>
Hi Weijie,
On Wed, 3 Aug 2022 at 21:40, Weijie Gao wrote:
>
> This add CLK_XTAL macro and flag to mediatek clock driver common part,
> to make thi SoC that has clock directlly connect to XTAL working.
>
> Signed-off-by: Weijie Gao
> ---
> drivers/clk/mediatek/clk-mtk.c | 3 +++
>
On Wed, 3 Aug 2022 at 21:40, Weijie Gao wrote:
>
> The verification code of gfh header for NAND and non-NAND are identical.
> It's better to define a individual function to reduce redundancy.
>
> Signed-off-by: Weijie Gao
> ---
> tools/mtk_image.c | 51
On Wed, 3 Aug 2022 at 21:39, Weijie Gao wrote:
>
> This patch adds pinctrl and gpio support for MT7986 SoC
>
> Signed-off-by: Weijie Gao
> ---
> drivers/pinctrl/mediatek/Kconfig | 4 +
> drivers/pinctrl/mediatek/Makefile | 1 +
> drivers/pinctrl/mediatek/pinctrl-mt7986.c |
On Wed, 3 Aug 2022 at 21:39, Weijie Gao wrote:
>
> This patch adds pinctrl and gpio support for MT7981 SoC
>
> Signed-off-by: Weijie Gao
> ---
> drivers/pinctrl/mediatek/Kconfig |4 +
> drivers/pinctrl/mediatek/Makefile |1 +
> drivers/pinctrl/mediatek/pinctrl-mt7981.c
+Tom Rini
Hi Martin,
On Thu, 4 Aug 2022 at 00:22, Martin Bonner wrote:
>
> On Wed, 3 Aug 2022 at 19:14, Simon Glass wrote:
>>
>> Hi Martin,
>>
>> On Wed, 3 Aug 2022 at 04:05, Martin Bonner wrote:
>> >
>> > I and my colleagues have a number of patches we would like to
>> > contribute back to
On Wed, 3 Aug 2022 at 21:41, Weijie Gao wrote:
>
> Add new filed for MediaTek ARM platform
files
>
> Signed-off-by: Weijie Gao
> ---
> MAINTAINERS | 5 +
> 1 file changed, 5 insertions(+)
Reviewed-by: Simon Glass
Hi Weijie,
On Wed, 3 Aug 2022 at 21:35, Weijie Gao wrote:
>
> This patch adds eMMC and SDXC support for MediaTek MT7981/MT7986 SoCs
Add eMMC and SDXC support for MediaTek MT7981/MT7986 SoCs.
(describe your changes in imperative mood)
>
> Signed-off-by: Weijie Gao
> ---
>
Since both pm8916.c and pm8916_gpio.c are already supporting multiple
Qcom SoCs, it makes sense to rename these drivers to pmic_qcom.c and
qcom_pmic_gpio.c respectively. Also, these driver can be extended to
support additional functionality if required for other Qcom SoCs.
Along with this import
PMIC GPIOs are special GPIOs which are accessible through SPMI bus. So
add corresponding DT nodes.
Signed-off-by: Sumit Garg
---
arch/arm/dts/qcs404-evb.dts | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts
For USB3 host controller to detect devices on the bus it is required to
enable a PMIC GPIO: usb_vbus_boost_pin. So enable that during board
specific initialization.
And since this PMIC GPIO parsing is quite u-boot specific, so add a
DT override to qcs404-evb-uboot.dtsi to represent
GPIO LV (low voltage)/MV (medium voltage) subtypes have different
features and register mappings than 4CH/8CH subtypes. Add support
for LV and MV subtypes.
With GPIO LV/MV subtype available, add "qcom,pms405-gpio" compatible
which requires support for GPIO MV subtype.
Signed-off-by: Sumit Garg
QCS404 SoC provides support for two USB controllers: one USB3 and the
other one being USB2. The USB3 controller supports further 2 PHY: one high
speed PHY and the other super speed PHY. The USB2 controller supports a
single high speed PHY. So add corresponding DT nodes.
Signed-off-by: Sumit Garg
Hi,
On Wed, 27 Jul 2022 at 13:52, Sumit Garg wrote:
>
> This is an initial step towards achieving complete Linux DT sync on Qcom
> SoCs/boards. It syncs up DT compatibles for pinctrl and GPIO drivers.
>
> Changes in v2:
> - Separate patch for CONFIG_SDM845 check removal.
> - Fix pinctrl DT
Hi Weijie,
On Wed, 3 Aug 2022 at 21:37, Weijie Gao wrote:
>
> The predefined NAND headers take too much spaces in the mtk_image.c.
> Moving them into a new file can significantly improve the readability of
> both mtk_image.c and the new mtk_nand_headers.c.
>
> This is a preparation for adding
Hi Weijie,
On Wed, 3 Aug 2022 at 21:41, Weijie Gao wrote:
>
> This patch adds more nand headers in two new types:
> 1. HSM header, used for spi-nand thru SNFI interface
> 2. SPIM header, used for spi-nand thru spi-mem interface
>
> The original nand header is renamed to AP header.
>
>
Hi Weijie,
On Wed, 3 Aug 2022 at 21:40, Weijie Gao wrote:
>
> This patch adds clock driver support for MediaTek MT7986 SoC
>
> Signed-off-by: Weijie Gao
> ---
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt7986.c | 671 +
>
Hi Weijie,
On Wed, 3 Aug 2022 at 21:36, Weijie Gao wrote:
>
> Using a single soc id to control different initialization and TX/RX flow
> for all SoCs is not extensible if more hardware variations are added in
> the future.
>
> This patch introduces a struct to replace the original mtk_soc to
Signed-off-by: Sumit Garg
---
drivers/phy/Kconfig | 15 +--
drivers/phy/Makefile | 3 +--
drivers/phy/qcom/Kconfig | 13 +
drivers/phy/qcom/Makefile | 2 ++
drivers/phy/{ =>
QCS404 SoC supports two types of PHY, one supports high speed mode or
USB2 PHY and the other supports super speed mode or USB3 PHY. So add
corresponding PHY drivers.
Signed-off-by: Sumit Garg
---
drivers/phy/qcom/Kconfig| 16 ++
drivers/phy/qcom/Makefile | 2 +
Since the base functionality remains the same for a reset driver on Qcom
SoCs, so leverage that to convert ipq4019 specific reset driver to a
generic Qcom reset driver. With that one just need to provide SoC specific
reset table.
Signed-off-by: Sumit Garg
---
drivers/reset/Kconfig
This series add support for USB on QCS404 SoC. USB support have
dependencies on PHY, reset and PMIC GPIO drivers, so corresponding
support has been added. There are also some renaming/reorganising
patches (#1, #3 and #9) which tries to generalize drivers support
for Qcom SoCs.
- Patch #1 moves all
All `sm efuseread/efusewrite` commands exit with an error, even if the fuse
have actually been dealt with correctly.
This is because the smc call return the size it actually processed but this
result is checked against 0.
Return failure in do_efuse_read/write if the return value of
On 03.08.22 13:00, Pali Rohár wrote:
Move U-Boot specific device tree property u-boot,dm-pre-reloc into U-Boot
specific device tree include file armada-xp-theadorable-u-boot.dtsi.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Tested-by: Stefan Roese
Thanks,
Stefan
---
On 03.08.22 13:00, Pali Rohár wrote:
Set u-boot,dm-pre-reloc for /soc/, /soc/internal-regs/ and nodes as
it is required on every 32-bit Armada SoCs. And set also u-boot,dm-pre-reloc
for when going to boot from SPI because otherwise SPL SPI drivers do
not load.
Signed-off-by: Pali Rohár
Hi Weijie,
On Wed, 3 Aug 2022 at 21:35, Weijie Gao wrote:
>
> This patch adds general board files based on MT7981 SoCs.
"Add general board files..." - same for other patches.
Are the dts files from a particular Linux version?
>
> Signed-off-by: Weijie Gao
> ---
> arch/arm/dts/Makefile
On Wed, 3 Aug 2022 at 21:36, Weijie Gao wrote:
>
> This patch adds support for PDMA v2 hardware. The PDMA v2 has extended the
> DMA descriptor to 8-words, and some of its fields have changed comparing
> to the v1 hardware.
>
> Signed-off-by: Weijie Gao
> ---
> drivers/net/mtk_eth.c | 51
Hi Weijie,
On Wed, 3 Aug 2022 at 21:36, Weijie Gao wrote:
>
> The baud clock on some platform may change due to assigned-clock-parent
> set in DT. In current flow the baud clock is only retrieved during probe
> stage. If the parent of the source clock changes after probe stage, the
> setbrg will
Hi Weijie,
On Wed, 3 Aug 2022 at 21:38, Weijie Gao wrote:
>
> This patch adds support for spi-mem controller found on newer MediaTek SoCs
> This controller supports Single/Dual/Quad SPI mode.
>
> Signed-off-by: SkyLake.Huang
> ---
> drivers/spi/Kconfig| 8 +
> drivers/spi/Makefile |
On Wed, 3 Aug 2022 at 21:36, Weijie Gao wrote:
>
> This patch is a preparation for adding a new version of PDMA of which the
> DMA descriptor fields has changed. Using bitfields will result in a complex
> modification. Convert bitfields to u32 units can solve this problem easily.
>
>
Hi Weijie,
On Wed, 3 Aug 2022 at 21:38, Weijie Gao wrote:
>
> This patch adds support for MediaTek I2C interface
>
> Signed-off-by: Weijie Gao
> ---
> drivers/i2c/Kconfig | 9 +
> drivers/i2c/Makefile | 1 +
> drivers/i2c/mtk_i2c.c | 822 ++
> 3
On Wed, 3 Aug 2022 at 21:38, Weijie Gao wrote:
>
> Add both hardware and software i2c support for mt7622.
>
> Signed-off-by: Weijie Gao
> ---
> arch/arm/dts/mt7622-rfb.dts | 18 ++
> arch/arm/dts/mt7622.dtsi| 24
> 2 files changed, 42 insertions(+)
Hi Stefan,
On Thu, 4 Aug 2022 at 01:50, Stefan Herbrechtsmeier
wrote:
>
> Hi Simon,
>
> Am 03.08.2022 um 20:14 schrieb Simon Glass:
> > Hi Stefan,
> >
> > On Tue, 2 Aug 2022 at 07:45, Stefan Herbrechtsmeier
> > wrote:
> >>
> >> Hi Simon,
> >>
> >> Am 02.08.2022 um 14:41 schrieb Simon Glass:
>
On Wed, 3 Aug 2022 at 21:38, Weijie Gao wrote:
>
> This patch adds a pinctrl header for common pinconf parameters such as
> pull-up/pull-down resistors and drive strengths.
>
> Signed-off-by: Weijie Gao
> ---
> include/dt-bindings/pinctrl/mt65xx.h | 41
> 1 file
Hi Weijie,
On Wed, 3 Aug 2022 at 21:39, Weijie Gao wrote:
>
> The mtk clock framework in u-boot uses array index for searching clock
> parent (kernel uses strings for search), so we need to specify a special
> clock with ID=0 for CLK_XTAL in u-boot.
>
> In the mt7622/mt7629 clock tree, the
Hi Weijie,
On Wed, 3 Aug 2022 at 21:40, Weijie Gao wrote:
>
> This patch adds clock driver support for MediaTek MT7981 SoC
>
> Signed-off-by: Weijie Gao
> ---
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt7981.c | 682 +
>
On Wed, 3 Aug 2022 at 21:39, Weijie Gao wrote:
>
> This patch adds infrasys clock mux support for mediatek clock drivers.
>
> Signed-off-by: Weijie Gao
> ---
> drivers/clk/mediatek/clk-mtk.c | 72 ++
> drivers/clk/mediatek/clk-mtk.h | 4 +-
> 2 files changed, 75
Signed-off-by: Sumit Garg
---
drivers/reset/reset-qcom.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/reset/reset-qcom.c b/drivers/reset/reset-qcom.c
index 40f436ede4..94315e76d5 100644
--- a/drivers/reset/reset-qcom.c
+++
Add support for USB controller and PHY clocks for QCS404 SoC.
Signed-off-by: Sumit Garg
---
arch/arm/mach-snapdragon/clock-qcs404.c | 35 +++
.../include/mach/sysmap-qcs404.h | 17 +
2 files changed, 52 insertions(+)
diff --git
Signed-off-by: Sumit Garg
---
arch/arm/dts/qcs404-evb.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts
index 09687e1fd3..1b280efff6 100644
--- a/arch/arm/dts/qcs404-evb.dts
+++ b/arch/arm/dts/qcs404-evb.dts
@@ -54,6 +54,12 @@
Drivers like USB, ethernet etc. uses ".enable" hook to enable clocks.
So add corresponding support for Qcom clock drivers.
Signed-off-by: Sumit Garg
---
arch/arm/mach-snapdragon/clock-apq8016.c| 5 +
arch/arm/mach-snapdragon/clock-apq8096.c| 5 +
Enable USB config options along with its dependencies like PHY, RESET,
PMIC GPIO etc. config options.
Signed-off-by: Sumit Garg
---
configs/qcs404evb_defconfig | 18 ++
1 file changed, 18 insertions(+)
diff --git a/configs/qcs404evb_defconfig b/configs/qcs404evb_defconfig
index
On 03.08.22 13:00, Pali Rohár wrote:
For future changes it is needed for have spi0 device tree reference in
every mvebu soc dts file even when it is unused.
Signed-off-by: Pali Rohár
---
arch/arm/dts/armada-7040.dtsi | 3 +++
arch/arm/dts/armada-8040.dtsi | 3 +++
arch/arm/dts/cn9130.dtsi
On 03.08.22 13:00, Pali Rohár wrote:
Move U-Boot specific device tree property u-boot,dm-pre-reloc into U-Boot
specific device tree include file armada-38x-controlcenterdc-u-boot.dtsi.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
On 03.08.22 13:00, Pali Rohár wrote:
Replace it by including of mvebu-u-boot.dtsi file. When board does not use
-u-boot.dtsi then mvebu-u-boot.dtsi is included automatically by makefile
scripts/Makefile.lib.
Signed-off-by: Pali Rohár
---
arch/arm/dts/armada-370-xp.dtsi | 1 -
On Thursday 04 August 2022 16:51:47 Stefan Roese wrote:
> On 03.08.22 13:00, Pali Rohár wrote:
> > For future changes it is needed for have spi0 device tree reference in
> > every mvebu soc dts file even when it is unused.
> >
> > Signed-off-by: Pali Rohár
> > ---
> >
Hi Michal,
On Thu, 4 Aug 2022 at 11:58, Michal Suchanek wrote:
>
> Explain when devices should get activated.
>
> Signed-off-by: Michal Suchanek
> ---
> doc/develop/driver-model/design.rst | 22 --
> 1 file changed, 20 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass
Hi Michal,
On Thu, 4 Aug 2022 at 11:59, Michal Suchanek wrote:
>
> When probing a device fails NULL pointer is returned, and other devices
> cannot be iterated. Skip to next device on error instead.
>
> Fixes: 6494d708bf ("dm: Add base driver model support")
> Signed-off-by: Michal Suchanek
>
Hi Heinrich,
On Wed, 3 Aug 2022 at 23:53, Heinrich Schuchardt wrote:
>
>
>
> On 8/3/22 20:13, Simon Glass wrote:
> > Hi Heinrich,
> >
> > I am seeing this:
> >
> > https://source.denx.de/u-boot/custodians/u-boot-dm/-/jobs/477636
>
> The EFI sub-system recorded successful execution of the test.
>
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