Hi Tom,
On Thu, Aug 30, 2012 at 4:25 PM, Tom Rini tr...@ti.com wrote:
On Thu, Aug 30, 2012 at 10:42:11PM +0200, Pavel Machek wrote:
Hi!
spl_ram_load_image... will I need to create some kind of #ifdef? Or
would #ifdef BOOT_DEVICE_RAM do the trick?
Good point, yes, we should
Hi Marek,
On Fri, 2012-09-14 at 19:02 +0200, Marek Vasut wrote:
Dear dingu...@altera.com,
From: Dinh Nguyen dingu...@altera.com
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Applied on top of trini/WIP/spl-improvements v6
Test building edminiv2_config
Hi Albert,
On Fri, 2013-07-05 at 23:04 +0200, ZY - albert.u.boot wrote:
Hi dingu...@altera.com,
On Tue, 2 Jul 2013 17:00:18 -0500, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Because the SOCFPGA platform will include support for Cyclone V and
Arria V FPGA parts
email address.
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v2:
- Fixed the long subject of the patch
- Consolidated the reset_manager structure
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v2:
- Fixed the word wrap issue within patch
Changes for v3:
- Fixed the long subject of the patch
Changes for v4:
- Added
w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v2:
- Fixed the word wrap issue within patch
Changes for v3:
- Fixed the long subject of the patch
- Fixed
for v5:
- Updated the license header for reset_manager.c
- Updated the subject
Re-org with latest changes on top.
Acked-by: Dinh Nguyen dingu...@altera.com
Dinh
---
board/altera/socfpga/pinmux_config.c | 214
++
board/altera/socfpga/pinmux_config.h
-by: Chin Liang See cl...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
---
Changes for v3
- Removed unused macro in freeze_controller.h
Changes for v2
- Removed FREEZE_CONTROLLER_FSM_HW
- Removed the get_timer_count_masked
This commit is an add-on to f6c4191f. There are a few other registers where
consecutive writes must have a delay.
Signed-off-by: Dinh Nguyen dingu...@altera.com
---
drivers/net/designware.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/designware.c b
448 Bit 4.
Register 459 Bits 0-3.
Reviewd-by: Matthew Gerlach mgerl...@altera.com
Signed-off-by: Dinh Nguyen dingu...@altera.com
---
drivers/net/designware.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
Hi Charles,
On 02/26/2014 01:42 AM, Charles Manning wrote:
On Wednesday 26 February 2014 19:16:37 Michal Simek wrote:
On 02/26/2014 02:17 AM, Charles Manning wrote:
Like many platforms, the Altera socfpga platform requires that the
preloader be signed in a certain way or the built-in boot ROM
Hi Wolfgang,
On Mon, 2014-01-13 at 22:08 +0100, ZY - wd wrote:
Dear Albert,
In message 20140113173924.684ce548@lilith you wrote:
Actually these Cc will be helpful when using git send-email. It will
auto cc to these mailing list when the patch is send out for review
(instead
On Sun, 21 Sep 2014, Marek Vasut wrote:
Enable support for the DWC2 USB controller.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w
-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
README| 3 +
drivers/usb
On Tue, Sep 23, 2014 at 2:55 PM, Dinh Nguyen
dingu...@opensource.altera.com wrote:
On Sun, 21 Sep 2014, Marek Vasut wrote:
Enable support for the DWC2 USB controller.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert
(socfpga_cyclone5.h), but there are more
to come.
This is necessary due to various features of the boards, which
unfortunatelly cannot be autodetected.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b
On 09/26/2014 02:29 AM, Marek Vasut wrote:
On Tuesday, September 23, 2014 at 11:59:28 PM, Dinh Nguyen wrote:
btw. please try to trim down the content of the patch when replying only to
the
relevant part, so others don't have to look up the relevant bits among
billions
of lines
Hi Marek,
On 10/7/14, 7:45 AM, Marek Vasut wrote:
Hey,
given that we now have most of the u-boot socfpga stuff in mainline, I
decided
it would be a good idea to list what we're still missing and we should also
decide how to move on now.
Thanks for all of your hard work on this!
Hi Marek,
On 10/22/14, 1:18 PM, Marek Vasut wrote:
This is not used anywhere, remove it.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Vince Bridgers vbrid...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc
On Thu, Sep 11, 2014 at 2:46 AM, Wolfgang Denk w...@denx.de wrote:
Dear Michal,
In message 54112b64.5010...@monstr.eu you wrote:
I am not sure if you need to have separate repo to work like this.
I am keeping zynq patches in my microblaze repo and sending pull request
to Albert
(or Tom
On Wed, Sep 10, 2014 at 6:33 PM, Marek Vasut ma...@denx.de wrote:
Hello,
I'd be interested in maintaining u-boot-socfpga repository. So far, we don't
have a repo for this platform and there is a large flurry of patches flying
around without any kind of central point for them. I'd like to get
On 09/11/2014 11:51 AM, Marek Vasut wrote:
On Thursday, September 11, 2014 at 06:14:55 PM, Dinh Nguyen wrote:
On Thu, Sep 11, 2014 at 2:46 AM, Wolfgang Denk w...@denx.de wrote:
Dear Michal,
In message 54112b64.5010...@monstr.eu you wrote:
I am not sure if you need to have separate repo
On 09/11/2014 12:14 PM, Tom Rini wrote:
On Thu, Sep 11, 2014 at 11:14:55AM -0500, Dinh Nguyen wrote:
On Thu, Sep 11, 2014 at 2:46 AM, Wolfgang Denk w...@denx.de wrote:
Dear Michal,
In message 54112b64.5010...@monstr.eu you wrote:
I am not sure if you need to have separate repo to work like
On 09/12/2014 12:25 AM, Wolfgang Denk wrote:
Dear Dinh,
In message 54122de5.1080...@opensource.altera.com you wrote:
Understood...You have just lit a fire in our arses! We have added a
resource internally, Vince Bridgers, to help us upstream more u-boot
support. Also, now that Linux
On 09/12/2014 02:46 PM, Wolfgang Denk wrote:
Dear Dinh,
In message 54133b22.2090...@opensource.altera.com you wrote:
So I suggest we create u-boot-socfpga now, as this will be needed
in any case when any significant amount of patches is coming in for
mainline.
For now, we assing Marek as
On 09/12/2014 04:05 PM, David Hawkins wrote:
Hi guys,
I'm going to jump in here with an end-user's perspective,
along with an offer of assistance/contribution.
I'm interested in using Altera's SOCs in my designs.
Altera guys - if you look over on the Altera Forum,
you will see that I am
On 09/12/2014 05:14 PM, Wolfgang Denk wrote:
Dear Dinh,
In message 54136276.6040...@opensource.altera.com you wrote:
To get patches or new code into U-Boot mainline, these have to be
submitted to the U-Boot mailing list (among other purposes for
archival and that they get stored in the
Hi David,
On 9/13/14, 12:24 PM, David Hawkins wrote:
Hi Dinh,
Up until now I have avoided any SoC development kits as
I considered the software support to not have matured
enough. I consider mature code to be code that I can
checkout from mainline, where mainline is U-Boot via the
Denx
Hi Wolfgang,
On 9/12/14, 5:51 PM, Wolfgang Denk wrote:
Dear Dinh,
In message 541373ad.4020...@opensource.altera.com you wrote:
Then I vote for myself as the custodian for u-boot-socfpga. By the way,
May I ask what made you change your mind like that? First you wrote
that Vince was
On 09/15/2014 06:05 AM, Marek Vasut wrote:
From: Pavel Machek pa...@denx.de
Remove this symbol from configs, since it's unused.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc
from it.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Cc: Joe Hershberger joe.hershber
...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Cc: Pantelis Antoniou pa...@antoniou
On 09/15/2014 06:06 AM, Marek Vasut wrote:
From: Pavel Machek pa...@denx.de
This adds watchdog disable. It is neccessary for running Linux kernel.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu
On 09/15/2014 06:06 AM, Marek Vasut wrote:
The inlining is done by GCC whe needed, there is no need to do it
s/whe/when.
Acked-by: Dinh Nguyen dingu...@opensource.altera.com
thanks...
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint
On 09/15/2014 06:06 AM, Marek Vasut wrote:
Add some stub defines, which are used by the clock code, but are
missing from the auto-generated header file for the SoCFPGA family.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
.
Signed-off-by: Pavel Machek pa...@denx.de
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
On 09/15/2014 06:06 AM, Marek Vasut wrote:
Pull out functions to read frequency of Main clock VCO and
PLL clock VCO as the code is duplicated multiple times.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud
Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
drivers/mmc/socfpga_dw_mmc.c | 15 +++
1 file changed
...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/timer.c | 2 ++
include/configs/socfpga_cyclone5.h | 2 --
2 files changed, 2
On 09/16/2014 08:18 AM, Pavel Machek wrote:
Hi!
On Mon 2014-09-15 13:05:53, Marek Vasut wrote:
This entire RFC series is the first stab at making SoCFPGA usable with
mainline U-Boot again. There are still some bits missing, but in general,
this allows me to use mainline U-Boot on my SoCFPGA
the
correctness of the code is easier to inspect.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w...@denx.de
Acked-by: Pavel Machek pa...@denx.de
On 09/16/2014 04:46 PM, Marek Vasut wrote:
On Tuesday, September 16, 2014 at 11:35:38 PM, dinguyen wrote:
On Tue, 16 Sep 2014, Marek Vasut wrote:
On Tuesday, September 16, 2014 at 06:28:52 PM, Dinh Nguyen wrote:
On 09/16/2014 08:18 AM, Pavel Machek wrote:
Hi!
On Mon 2014-09-15 13:05:53
On 09/16/2014 04:55 PM, Marek Vasut wrote:
On Tuesday, September 16, 2014 at 11:29:45 PM, dinguyen wrote:
On Tue, 16 Sep 2014, Marek Vasut wrote:
On Tuesday, September 16, 2014 at 06:28:52 PM, Dinh Nguyen wrote:
On 09/16/2014 08:18 AM, Pavel Machek wrote:
Hi!
On Mon 2014-09-15 13:05:53
On 11/5/13 11:46 AM, Jagannadha Sutradharudu Teki wrote:
Zynq uart controller support two serial ports like
CONFIG_ZYNQ_SERIAL_UART0 and CONFIG_ZYNQ_SERIAL_UART1
enabled both so-that the respective board will define
these macros based on their usage.
Signed-off-by: Jagannadha Sutradharudu
On 11/5/13 11:46 AM, Jagannadha Sutradharudu Teki wrote:
Zynq qspi controller driver supports single bus
with singe chipselect.
Zynq qspi can be operated in below connection modes
- single qspi
- dual qspi, with dual stacked
- dual qspi, with dual parallel
Signed-off-by: Jagannadha
On 11/5/13 11:46 AM, Jagannadha Sutradharudu Teki wrote:
Zynq qspi controller driver supports single bus
with singe chipselect.
Zynq qspi can be operated in below connection modes
- single qspi
- dual qspi, with dual stacked
- dual qspi, with dual parallel
Signed-off-by: Jagannadha
On 11/5/13 11:46 AM, Jagannadha Sutradharudu Teki wrote:
Zynq uart controller support two serial ports like
CONFIG_ZYNQ_SERIAL_UART0 and CONFIG_ZYNQ_SERIAL_UART1
enabled both so-that the respective board will define
these macros based on their usage.
Signed-off-by: Jagannadha Sutradharudu
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA512
On 11/6/13 12:45 AM, Michal Simek wrote:
On 11/06/2013 05:17 AM, Dinh Nguyen wrote:
On 11/5/13 11:46 AM, Jagannadha Sutradharudu Teki wrote:
Zynq uart controller support two serial ports like
CONFIG_ZYNQ_SERIAL_UART0
On Tue, Nov 12, 2013 at 9:17 AM, Michal Simek mon...@monstr.eu wrote:
On 11/12/2013 03:46 PM, Chin Liang See wrote:
Hi all,
On Tue, 2013-11-12 at 11:17 +0100, Michal Simek wrote:
On 11/12/2013 10:56 AM, Detlev Zundel wrote:
Hi Michal,
On 11/11/2013 09:33 PM, Tom Rini wrote:
On
Hi Albert,
On Thu, 2012-10-04 at 21:54 +0200, ZY - albert.u.boot wrote:
Hi dingu...@altera.com,
On Thu, 4 Oct 2012 10:46:02 -0600, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Add minimal support for Altera's SOCFPGA Cyclone 5 hardware.
Signed-off-by: Dinh
Hi Vikram,
On Tue, 2012-10-23 at 15:49 +0530, Vikram Narayanan wrote:
Cleanups for SPL/socfpga.
Cc: Dinh Nguyen dingu...@altera.com
Vikram Narayanan (2):
arm/socfpga: Remove timer_init from spl_board_init
socfpga/spl: Remove malloc.h
Do you need to split up the patches? Otherwise
Hi Marek,
Have you been able to successfully boot Linux using the mainline uboot?
I cannot seem to be able to boot linux on the C5 SocDK.
It starts to boot linux, but then reboots after a bit back into u-boot.
So I commented out #define CONFIG_HW_WATCHDOG in
include/configs/socfpga_cyclone5.h.
On 11/06/2014 05:40 PM, Anatolij Gustschin wrote:
Hi Dinh,
On Thu, 6 Nov 2014 17:03:48 -0600
Dinh Nguyen dingu...@opensource.altera.com wrote:
Hi Marek,
Have you been able to successfully boot Linux using the mainline uboot?
I cannot seem to be able to boot linux on the C5 SocDK
+CC: Graham Moore
On 11/07/2014 09:26 AM, Stefan Roese wrote:
Hi Dinh, Hi Vince!
a quick question for you:
On 07.11.2014 16:04, Marek Vasut wrote:
snip
diff --git a/drivers/spi/cadence_qspi_apb.c
b/drivers/spi/cadence_qspi_apb.c new file mode 100644
index 000..00a115f
---
+CC: Graham Moore
On 11/10/2014 04:47 AM, Pavel Machek wrote:
On Fri 2014-11-07 18:26:05, Stefan Roese wrote:
Hi Simon,
On 07.11.2014 18:21, Simon Glass wrote:
+ qspi: spi@ff705000 {
+ compatible = cadence,qspi;
+ #address-cells =
+CC: Matthew Gerlach
Not sure why the original submitter was left on this response.
On 12/3/14, 11:36 AM, Simon Glass wrote:
Hi,
On 3 December 2014 at 06:48, Pavel Machek pa...@ucw.cz wrote:
Hi!
Altera Arria10 SOCFPGA Pin Configuration Bindings
This document describes device tree
Hi Simon,
On 02/05/2015 10:41 PM, Simon Glass wrote:
Remove driver model CONFIGs from the board config headers and use Kconfig
instead.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v2: None
configs/socfpga_socrates_defconfig | 3 +++
include/configs/socfpga_common.h
On 1/14/15 5:45 PM, Marek Vasut wrote:
On Wednesday, January 14, 2015 at 05:40:48 PM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com
You might want to check common/spl/spl.c , which
On 01/14/2015 05:54 PM, Marek Vasut wrote:
On Wednesday, January 14, 2015 at 05:40:53 PM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
s_init will map SDRAM to 0x0.
Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com
Hi!
[...]
+void
Hi Marek,
On 01/14/2015 05:58 PM, Marek Vasut wrote:
On Wednesday, January 14, 2015 at 05:40:55 PM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Add a function to relocate the stack from OCRAM to SDRAM.
Hi,
is this functionality really needed
On 01/15/2015 04:00 PM, Marek Vasut wrote:
On Thursday, January 15, 2015 at 08:19:15 PM, Dinh Nguyen wrote:
Hi Marek,
Hi Dinh,
On 01/14/2015 05:58 PM, Marek Vasut wrote:
On Wednesday, January 14, 2015 at 05:40:55 PM,
dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu
On 01/14/2015 05:34 PM, Marek Vasut wrote:
On Wednesday, January 14, 2015 at 05:40:41 PM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Hi!
This adds the code to configure the SDRAM controller that is found in the
SoCFGPA Cyclone5 and Arria5
USB port and SD card must be installed
for this to work.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@opensource.altera.com
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Stefan Roese s...@denx.de
Cc: Vince Bridgers vbrid
On 12/31/14 1:14 PM, Marek Vasut wrote:
Drop the _cyclone5 suffix from socfpga_cyclone5.c since this file
will contain Arria 5 support as well.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@opensource.altera.com
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Pavel
On 12/31/14 1:14 PM, Marek Vasut wrote:
Replace multiple spaces with a single tab.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@opensource.altera.com
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Stefan Roese s...@denx.de
Cc
rework.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@opensource.altera.com
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Stefan Roese s...@denx.de
Cc: Vince Bridgers vbrid...@opensource.altera.com
---
board/altera/socfpga/pll_config.h
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Stefan Roese s...@denx.de
Cc: Vince Bridgers vbrid...@opensource.altera.com
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_arria5.dtsi | 34
arch/arm/dts
On 12/31/14 1:14 PM, Marek Vasut wrote:
Add support for the Altera Arria V development kit.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@opensource.altera.com
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Stefan Roese s...@denx.de
On 12/31/14 1:15 PM, Marek Vasut wrote:
Zap this unused empty function, no point in having it.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@opensource.altera.com
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Stefan Roese s
On 12/31/14 1:14 PM, Marek Vasut wrote:
Since all boards now have a DT, instead of hard-coding the board
name into the U-Boot binary, read the board name from DT model
property.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@opensource.altera.com
Cc: Dinh Nguyen dingu
On 12/31/14 1:14 PM, Marek Vasut wrote:
Sync SoCFPGA Cyclone V development kit pinmux configuration with
Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@opensource.altera.com
Cc: Dinh Nguyen dingu
On Thu, 19 Feb 2015, Marek Vasut wrote:
+cc: John Youn
John took over the maintainership of the DWC2 driver in linux as Paul
Zimmerman is no longer at Synopsys.
On Monday, February 16, 2015 at 07:28:45 PM, Stephen Warren wrote:
Marek,
Hello Stephen,
Following on from my Google+ post
On 02/07/2015 07:34 AM, Marek Vasut wrote:
On Thursday, February 05, 2015 at 10:16:59 PM, Dinh Nguyen wrote:
On 01/14/2015 05:54 PM, Marek Vasut wrote:
[...]
+ /*
+ * Private components security
+ * U-Boot : configure private timer, global timer and cpu
+ * component access
On 02/09/2015 01:29 AM, Stefan Roese wrote:
Hi,
(added Marek to Cc)
On 07.02.2015 01:11, Simon Glass wrote:
Hi Dinh,
On 6 February 2015 at 16:36, Dinh Nguyen
dingu...@opensource.altera.com wrote:
Hi Simon,
On 02/05/2015 10:41 PM, Simon Glass wrote:
Remove driver model CONFIGs from
On 3/4/15 7:21 AM, Marek Vasut wrote:
On Monday, March 02, 2015 at 05:28:05 PM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com
---
arch/arm/cpu/armv7/socfpga/spl.c | 8
1 file
On 3/5/15 2:59 PM, Marek Vasut wrote:
On Wednesday, March 04, 2015 at 10:34:30 PM, Dinh Nguyen wrote:
On 03/04/2015 01:39 PM, Marek Vasut wrote:
On Wednesday, March 04, 2015 at 07:52:04 PM, Dinh Nguyen wrote:
On 03/04/2015 06:39 AM, Marek Vasut wrote:
On Monday, March 02, 2015 at 05:27:50
On 3/31/15 3:48 PM, Pavel Machek wrote:
On Mon 2015-03-30 17:01:18, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
commit 07d30b6c3129 arm: socfpga: Sync Cyclone V DK pinmux configuration
incorrectly set the muxing for UART0 on the Cyclone V DK
On 03/04/2015 06:39 AM, Marek Vasut wrote:
On Monday, March 02, 2015 at 05:27:50 PM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Add a section of SRAM to the SPL linker file.
Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com
Hi!
Can
On 03/04/2015 01:39 PM, Marek Vasut wrote:
On Wednesday, March 04, 2015 at 07:52:04 PM, Dinh Nguyen wrote:
On 03/04/2015 06:39 AM, Marek Vasut wrote:
On Monday, March 02, 2015 at 05:27:50 PM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Add
On 2/23/15 10:57 AM, Marek Vasut wrote:
On Monday, February 23, 2015 at 05:39:53 PM, Dinh Nguyen wrote:
On 2/23/15 10:37 AM, Dinh Nguyen wrote:
On 2/15/15 5:25 PM, Pavel Machek wrote:
Hi!
+#if ENABLE_BRINGUP_DEBUGGING
Could we get rid of this for initial merge?
Yeah, it can be removed
Hi Marek,
On 03/04/2015 07:16 AM, Marek Vasut wrote:
On Monday, March 02, 2015 at 05:28:03 PM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com
Why did you do this change please ?
Sorry
On 5/7/15 6:06 AM, Marek Vasut wrote:
On Thursday, May 07, 2015 at 01:03:28 PM, Pavel Machek wrote:
On Thu 2015-05-07 12:19:38, Marek Vasut wrote:
On Thursday, May 07, 2015 at 06:15:51 AM, Masahiro Yamada wrote:
Hi Marek,
Hi!
2015-05-07 12:25 GMT+09:00 Marek Vasut ma...@denx.de:
On
On 04/02/2015 08:54 PM, Marek Vasut wrote:
On Tuesday, March 31, 2015 at 12:01:16 AM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
This sets the CPU clocks to 925MHz and DDR to 400MHz, and the correct
CONFIG_HPS_MAINPLLGRP_VCO_NUMER should be 79
On 4/16/15 1:32 AM, Marek Vasut wrote:
On Wednesday, April 15, 2015 at 11:14:50 PM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Hello,
The following 2 patches adds the DDR controller driver that is in the
Altera SoCFPGA platform. This driver
On 04/11/2015 11:57 AM, Marek Vasut wrote:
On Tuesday, April 07, 2015 at 04:31:43 PM, Dinh Nguyen wrote:
On Fri, 3 Apr 2015, Marek Vasut wrote:
On Tuesday, March 31, 2015 at 12:01:11 AM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Add a stub
Hi Pavel,
On 04/17/2015 07:31 AM, Pavel Machek wrote:
Hi!
+#ifndef _SDRAM_H_
+#define _SDRAM_H_
+
+#ifndef __ASSEMBLY__
+
+/* function declaration */
You can delete this comment.
Ok...
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
+#define \
Hi Marek,
On Thu, Apr 2, 2015 at 9:00 PM, Marek Vasut ma...@denx.de wrote:
On Tuesday, March 31, 2015 at 08:41:46 AM, Wolfgang Denk wrote:
Dear dingu...@opensource.altera.com,
In message
1427752878-18426-2-git-send-email-dingu...@opensource.altera.com you
wrote:
...
+/* Register:
On Fri, 3 Apr 2015, Marek Vasut wrote:
On Tuesday, March 31, 2015 at 12:01:11 AM, dingu...@opensource.altera.com
wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Add a stub s_init function in the board file.
Why do you add this stub function ? The commit message should
On Fri, 3 Apr 2015, Marek Vasut wrote:
On Tuesday, March 31, 2015 at 11:07:57 PM, Pavel Machek wrote:
Hi!
On Mon 2015-03-30 17:01:14, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
Remap SDRAM to 0x0, and clear OCRAM's ECC in board_init_f
On 6/9/15 6:55 AM, Pavel Machek wrote:
Hi!
+struct sdram_prot_rule {
+uint64_tsdram_start; /* SDRAM start address */
+uint64_tsdram_end; /* SDRAM end address */
+uint32_trule; /* SDRAM protection rule number: 0-19 */
+int valid; /* Rule
On 05/28/2015 01:18 PM, Marek Vasut wrote:
On Thursday, May 28, 2015 at 05:41:26 PM, Dinh Nguyen wrote:
On 05/25/2015 08:23 AM, Wolfgang Denk wrote:
Dear Pavel,
In message 20150525123750.GD9943@amd you wrote:
+ ** All global variables that are explicitly initialized (including
On 05/25/2015 08:23 AM, Wolfgang Denk wrote:
Dear Pavel,
In message 20150525123750.GD9943@amd you wrote:
+ ** All global variables that are explicitly initialized (including
**
+ ** explicitly initialized to zero), are only initialized once, during
**
+ ** configuration
On 05/25/2015 08:23 AM, Wolfgang Denk wrote:
Dear Pavel,
In message 20150525123750.GD9943@amd you wrote:
+ ** All global variables that are explicitly initialized (including
**
+ ** explicitly initialized to zero), are only initialized once, during
**
+ ** configuration
On 5/21/15 6:35 PM, Marek Vasut wrote:
On Monday, May 18, 2015 at 09:36:48 PM, dingu...@opensource.altera.com wrote:
From: Dinh Nguyen dingu...@opensource.altera.com
This patch adds the DDR calibration portion of the Altera SDRAM driver.
Signed-off-by: Dinh Nguyen dingu
to start picking it up
so it can land in 2015.10 . Reviews and comments are welcome.
Thank you so much for putting this series together! For the whole series:
Acked-by: Dinh Nguyen dingu...@opensource.altera.com
Dinh
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/polution/pollution
Acked-by: Dinh Nguyen dingu...@opensource.altera.com
Thanks,
Dinh
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/altera = board/altera/socfpga/qts}/sequencer_defines.h
(100%)
Acked-by: Dinh Nguyen dingu...@opensource.altera.com
Thanks,
Dinh
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(-)
Acked-by: Dinh Nguyen dingu...@opensource.altera.com
Thanks,
Dinh
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/sequencer.h | 31 --
2 files changed, 5 insertions(+), 75 deletions(-)
Acked-by: Dinh Nguyen dingu...@opensource.altera.com
Thanks,
Dinh
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the nasty QTS generated macros
in board files and reducing the polution of the namespace.
s/polution/pollution
Acked-by: Dinh Nguyen dingu...@opensource.altera.com
Thanks,
Dinh
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