| TIMER_MODE_USERDEF )
Thanks and have a nice day!
Chin Liang
Direct Line: +604 - 636 8776
-Original Message-
From: Pavel Machek [mailto:pa...@denx.de]
Sent: Friday, August 31, 2012 1:00 AM
To: Marek Vasut
Cc: Tom Rini; albert.u.b...@aribaud.net; ZY - u-boot; dinh.li...@gmail.com;
Chin Liang
socfpga: Separating the configuration file for Virtual Target and
real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
---
include/configs/socfpga_cyclone5.h | 28 +---
1 files changed, 21 insertions(+), 7 deletions(-)
diff --git
socfpga: Adding System Manager driver which will configure the pin mux
for real hardware Cyclone V development kit (not Virtual Platform)
Signed-off-by: Chin Liang See cl...@altera.com
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/spl.c
socfpga: Consolidating reset code into reset_manager.c. Also separating
reset configuration for virtual target and real hardware Cyclone V
development kit
Signed-off-by: Chin Liang See cl...@altera.com
---
arch/arm/cpu/armv7/socfpga/Makefile |2 +-
arch/arm/cpu/armv7/socfpga
Hi Pavel,
On Fri, 2013-06-28 at 13:40 +0200, ZY - pavel wrote:
Hi!
socfpga: Adding System Manager driver which will configure the pin mux
for real hardware Cyclone V development kit (not Virtual Platform)
Signed-off-by: Chin Liang See cl...@altera.com
diff --git a/arch/arm/cpu
Hi Pavel,
On Fri, 2013-06-28 at 13:22 +0200, ZY - pavel wrote:
Hi!
socfpga: Separating the configuration file for Virtual Target and
real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
---
include/configs/socfpga_cyclone5.h | 28
Hi Pavel,
On Fri, 2013-06-28 at 13:44 +0200, ZY - pavel wrote:
Hi!
socfpga: Consolidating reset code into reset_manager.c. Also separating
reset configuration for virtual target and real hardware Cyclone V
development kit
Signed-off-by: Chin Liang See cl...@altera.com
+++ b
socfpga: Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
---
include/configs/socfpga_cyclone5.h | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git
socfpga: Adding System Manager driver which will
configure the pin mux for real hardware Cyclone V
development kit (not Virtual Platform)
Signed-off-by: Chin Liang See cl...@altera.com
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch/arm/cpu/armv7/socfpga/spl.c
socfpga: Consolidating reset code into reset_manager.c.
Also separating reset configuration for virtual target
and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
---
arch/arm/cpu/armv7/socfpga/Makefile |2 +-
arch/arm/cpu/armv7/socfpga
Hi Pavel,
On Mon, 2013-07-01 at 12:39 +0200, ZY - pavel wrote:
Hi!
--- /dev/null
+++ b/board/altera/socfpga_cyclone5/pinmux_config.c
@@ -0,0 +1,213 @@
+
+#include pinmux_config.h
+
+/* pin mux configuration data */
+unsigned long
Hi Pavel,
On Mon, 2013-07-01 at 12:42 +0200, ZY - pavel wrote:
On Fri 2013-06-28 16:20:48, Chin Liang See wrote:
socfpga: Adding System Manager driver which will
configure the pin mux for real hardware Cyclone V
development kit (not Virtual Platform)
Signed-off-by: Chin Liang See
Hi Wolfgang,
On Sat, 2013-06-29 at 00:47 +0200, ZY - wd wrote:
Dear Chin Liang See,
In message 1372451028.11240.2.ca...@drezykow-virtualbox.altera.com you
wrote:
socfpga: Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit
Please keep
Hi Pavel,
On Mon, 2013-07-01 at 12:46 +0200, ZY - pavel wrote:
Hi!
@@ -21,6 +21,7 @@
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
struct socfpga_reset_manager {
u32padding1;
socfpga: Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
---
include/configs/socfpga_cyclone5.h | 28 +---
1 file changed, 21 insertions(+), 7 deletions(-)
diff --git
socfpga: Consolidating reset code into reset_manager.c.
Also separating reset configuration for virtual target
and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
---
arch/arm/cpu/armv7/socfpga/Makefile |2 +-
arch/arm/cpu/armv7/socfpga
socfpga: Adding System Manager driver which
will configure the pin mux for real hardware Cyclone V
development kit (not Virtual Platform)
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
---
arch/arm/cpu/armv7/socfpga/Makefile|2 +-
arch
socfpga: Adding the generated pin mux
configuration by Preloader Generator tool
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
---
board/altera/socfpga_cyclone5/pinmux_config.c | 214
+
board/altera/socfpga_cyclone5/pinmux_config.h
socfpga: Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
---
Changes for v2:
- Fixed the word wrap issue within patch
Changes for v3:
- Fixed the long subject of the patch
Changes for v4
Consolidating reset code into reset_manager.c.
Also separating reset configuration for virtual target
and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Adding the generated pin mux
configuration by Preloader Generator tool
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
---
Changes for v2:
- Fixed the word
Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen
Dear Wolfgang,
On Tue, 2013-07-02 at 06:24 +0200, ZY - wd wrote:
Dear Chin Liang See,
In message 1372719771-4329-1-git-send-email-cl...@altera.com you wrote:
Adding the generated pin mux
configuration by Preloader Generator tool
In addition to the license issue, please chose
Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc
Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen
Adding the generated pin mux
configuration by Preloader Generator tool
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc: Albert
Consolidating reset code into reset_manager.c.
Also separating reset configuration for virtual target
and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen
Consolidating reset code into reset_manager.c.
Also separating reset configuration for virtual target
and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen
Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc
Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen
Adding the generated pin mux
configuration by Preloader Generator tool
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr...@ti.com
Cc: Albert
On Tue, 2013-08-06 at 11:00 -0500, Dinh Nguyen wrote:
On Tue, 2013-08-06 at 09:08 -0500, Chin Liang See wrote:
Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek
On Tue, 2013-08-06 at 11:03 -0500, Dinh Nguyen wrote:
On Tue, 2013-08-06 at 09:10 -0500, Chin Liang See wrote:
Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)
Signed-off-by: Chin Liang See cl...@altera.com
On Tue, 2013-08-06 at 11:04 -0500, Dinh Nguyen wrote:
On Tue, 2013-08-06 at 09:10 -0500, Chin Liang See wrote:
Adding the generated pin mux
configuration by Preloader Generator tool
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Cc: Wolfgang
Adding the generated pin mux configuration by Preloader
Generator tool
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Acked-by: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Acked-by: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC
Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Cc: Tom Rini tr
On Tue, 2013-08-06 at 11:01 -0500, Dinh Nguyen wrote:
On Tue, 2013-08-06 at 09:09 -0500, Chin Liang See wrote:
Consolidating reset code into reset_manager.c.
Also separating reset configuration for virtual target
and real hardware Cyclone V development kit
Signed-off-by: Chin Liang See
Consolidating reset code into reset_manager.c. Also
separating reset configuration for virtual target and
real hardware Cyclone V development kit
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Cc: Wolfgang Denk w...@denx.de
Cc: Pavel Machek pa...@denx.de
Cc
Hi Pavel,
On Thu, 2013-08-15 at 15:15 +0200, ZY - pavel wrote:
Hi!
Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa
Hi guys,
Wonder any updates on this? We plan to send the new patches only once
these existing patches are accepted. Appreciate for your helps again.
Chin Liang
On Thu, 2013-08-22 at 13:05 +0200, ZY - pavel wrote:
Hi!
Albert, Tom this patch has been here for a week, without any
Hi Pavel,
On Thu, 2013-09-05 at 13:10 +0200, ZY - pavel wrote:
Hi!
Wonder any updates on this? We plan to send the new patches only once
these existing patches are accepted. Appreciate for your helps
again.
Albert seems to be back, perhaps he'll us how he wants us to proceed?
Yup, I
Adding System Manager driver which will configure the
pin mux for real hardware Cyclone V development kit
(not Virtual Platform)
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Acked-by: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC
Adding the generated pin mux configuration by Preloader
Generator tool
Signed-off-by: Chin Liang See cl...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Acked-by: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh Nguyen dingu...@altera.com
Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Wolfgang Denk w
Hi Albert,
Would need your help to apply this patch too to u-boot-arm/master as
this patch has been a while ago. Thanks and have a nice day!
Chin Liang
On Wed, 2013-09-11 at 11:26 -0500, Chin Liang See wrote:
Adding the generated pin mux configuration by Preloader
Generator tool
Signed
Hi Albert,
Would need your help to apply this patch to u-boot-arm/master as this
patch has been a while ago. Thanks and have a nice day!
Chin Liang
On Wed, 2013-09-11 at 11:24 -0500, Chin Liang See wrote:
Adding System Manager driver which will configure the
pin mux for real hardware Cyclone
Hi Pavel,
On Thu, 2013-09-19 at 14:11 +0200, ZY - pavel wrote:
Hi!
Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external
Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Wolfgang Denk w
code, we still not yet to boot on real board yet.
That why I am working hard to get the code upstreamed asap. Of course,
appreciate your help too as you are very helpful.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Dinh
Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Wolfgang Denk w
Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during the configuration from propagating to external devices.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Wolfgang Denk w
On Mon, 2013-09-23 at 13:59 -0500, Dinh Nguyen wrote:
On Fri, 2013-09-20 at 00:08 -0500, Chin Liang See wrote:
diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c
b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
new file mode 100644
index 000..93ad22a
--- /dev/null
+++ b
Hi guys,
Any further comments on this? Thanks
Chin Liang
On Tue, 2013-09-24 at 09:49 -0500, Chin Liang See wrote:
Adding Freeze Controller driver. All HPS IOs need to be
in freeze state during pin mux or IO buffer configuration.
It is to avoid any glitch which might happen
during
Thanks Alexey.
Hi Heiko,
I believe this patch should be good for apply. Would need your help
then. :) Thanks
Chin Liang
On Wed, 2014-01-15 at 15:51 +, Alexey Brodkin wrote:
On Wed, 2014-01-15 at 09:45 -0600, Chin Liang See wrote:
Changes for v2
- Removed the function check_params
Hi Heiko,
On Thu, 2014-01-30 at 06:20 +0100, Heiko Schocher wrote:
Hello Chin,
Am 22.01.2014 16:37, schrieb Chin Liang See:
Thanks Alexey.
Hi Heiko,
I believe this patch should be good for apply. Would need your help
then. :) Thanks
Chin Liang
On Wed, 2014-01-15 at 15:51
Enhance the DesignWare I2C driver to support address length more
than 1 byte. This enhancement is required as some I2C slave
device such as EEPROM chip might have 16 bit address byte.
Signed-off-by: Chin Liang See cl...@altera.com
Acked-by: Alexey Brodkin alexey.brod...@synopsys.com
Cc: Tom Rini
Hi Albert,
As there are no further comments, would need your help to apply this
patch. Thanks and appreciate for your support.
Chin Liang
On Wed, 2013-12-18 at 16:23 -0600, Chin Liang See wrote:
To add the DesignWare watchdog driver support. It required
information such as register base
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Tom Rini tr...@ti.com
Cc
The IOCSR handoff files will be consumed by Scan Manager driver.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Signed-off
Hi Albert,
As there are no further comments, would need your help to apply this
patch. Thanks and appreciate for your support.
Chin Liang
On Wed, 2013-12-18 at 17:54 -0600, Chin Liang See wrote:
Clock Manager driver will be called to reconfigure all the
clocks setting based on user input
Hi Scott,
As there are no further comments, would need your help to apply this
patch. Thanks and appreciate for your support.
Chin Liang
On Wed, 2013-12-18 at 15:18 -0600, Chin Liang See wrote:
To add the Denali NAND driver support into U-Boot. It required
information such as register base
Hi Albert,
As there are no further comments, would need your help to apply this
patch. Thanks and appreciate for your support.
Chin Liang
On Wed, 2013-12-18 at 17:54 -0600, Chin Liang See wrote:
The pll_config.h will be consumed by Clock Manager driver
Signed-off-by: Chin Liang See cl
Hi Jagan,
As there are no further comments, would need your help to apply this
patch. Thanks and appreciate for your support.
Chin Liang
On Fri, 2014-01-10 at 11:39 -0600, Chin Liang See wrote:
To add the Cadence SPI driver support for Altera SOCFPGA. It
required information such as clocks
Dear Albert,
On Thu, 2014-02-13 at 10:45 +0100, ZY - albert.u.boot wrote:
Applied to u-boot-arm/master, thanks!
Note that arch/arm/cpu/armv7/socfpga/scan_manager.c had spurious empty
lines at the end; I fixed that.
Tom: as V1 and V2 were assigned to me, I reassigned this RESEND
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Tom Rini tr...@ti.com
Cc
Clock Manager driver will be called to reconfigure all the
clocks setting based on user input. The input are passed to
Preloader through handoff files
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w
Hi Albert,
On Thu, 2014-02-13 at 10:53 +0100, ZY - albert.u.boot wrote:
Hi Chin,
On Wed, 18 Dec 2013 17:54:33 -0600, Chin Liang See cl...@altera.com
wrote:
Clock Manager driver will be called to reconfigure all the
clocks setting based on user input. The input are passed to
Preloader
Hi Pavel,
Nice to hear from you again :)
On Fri, 2014-02-21 at 16:07 +0100, ZY - pavel wrote:
Hi!
+ /*
+* Check if the scan chain engine is inactive and the
+* WFIFO is empty before enabling the IO scan chain
+*/
+ if (SCAN_MGR_IO_SCAN_ENGINE_STATUS_IDLE
+
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Tom Rini tr...@ti.com
Cc
Hi Albert,
On Thu, 2014-02-13 at 10:35 +0100, ZY - albert.u.boot wrote:
Hi Chin,
On Wed, 18 Dec 2013 16:23:35 -0600, Chin Liang See cl...@altera.com
wrote:
To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file within include/configs folder.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Anatolij Gustschin ag...@denx.de
Cc: Albert Aribaud albert.u.b
Hi Masahiro,
On Fri, 2014-02-21 at 19:57 +0900, Masahiro Yamada wrote:
Hi Chin,
(adding Albert to Cc:)
Hi Scott,
As there are no further comments, would need your help to apply this
patch. Thanks and appreciate for your support.
Chin Liang
Panasonic SoCs are using Denali
Hi Albert,
On Fri, 2014-02-21 at 17:58 +0100, ZY - albert.u.boot wrote:
Hi Chin,
On Fri, 21 Feb 2014 10:00:08 -0600, Chin Liang See cl...@altera.com
wrote:
Hi Albert,
On Thu, 2014-02-13 at 10:35 +0100, ZY - albert.u.boot wrote:
Hi Chin,
On Wed, 18 Dec 2013 16:23:35 -0600
To add the Denali NAND driver support into U-Boot. It required
information such as register base address from configuration
header file within include/configs folder.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Artem Bityutskiy artem.bityuts...@linux.intel.com
Cc: David Woodhouse
To add the Denali NAND driver support into SOCFPGA. But it would
not enabled by default as Altera Cyclone V dev kit doesn't have
a NAND device on it.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Artem Bityutskiy artem.bityuts...@linux.intel.com
Cc: David Woodhouse david.woodho...@intel.com
To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file within include/configs folder.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Anatolij Gustschin ag...@denx.de
Cc: Albert Aribaud albert.u.b
To enable the DesignWare watchdog support at SOCFPGA Cyclone V
dev kit.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Anatolij Gustschin ag...@denx.de
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Heiko Schocher h...@denx.de
Cc: Tom Rini tr...@ti.com
---
Changes for v3
- Split to 2 series
Hi Michal,
On Fri, 2014-02-21 at 17:01 +0100, Michal Simek wrote:
Hi,
On 02/21/2014 04:26 PM, Chin Liang See wrote:
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See cl
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Tom Rini tr...@ti.com
Cc
Dear Wolfgang,
On Sat, 2014-02-22 at 09:42 +0100, ZY - wd wrote:
Dear Chin Liang See,
In message 1393022790-9296-1-git-send-email-cl...@altera.com you wrote:
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Tom Rini tr...@ti.com
Cc
Hi Michal,
On Mon, 2014-02-24 at 08:48 +0100, Michal Simek wrote:
On 02/21/2014 09:51 PM, Chin Liang See wrote:
To add the Denali NAND driver support into U-Boot. It required
information such as register base address from configuration
header file within include/configs folder
To add the Denali NAND driver support into U-Boot. It required
information such as register base address from configuration
header file within include/configs folder.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Artem Bityutskiy artem.bityuts...@linux.intel.com
Cc: David Woodhouse
Hi Michal,
On Mon, 2014-02-24 at 08:51 +0100, Michal Simek wrote:
On 02/21/2014 09:57 PM, Chin Liang See wrote:
To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file within include/configs folder
To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file within include/configs folder.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Anatolij Gustschin ag...@denx.de
Cc: Albert Aribaud albert.u.b
Hi Michal,
On Mon, 2014-02-24 at 08:52 +0100, Michal Simek wrote:
On 02/21/2014 09:57 PM, Chin Liang See wrote:
To enable the DesignWare watchdog support at SOCFPGA Cyclone V
dev kit.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Anatolij Gustschin ag...@denx.de
Cc: Albert
Hi Masahiro,
On Thu, 2014-02-27 at 23:35 +0900, Masahiro Yamada wrote:
Hello Chin,
+
+ nand-ecc.mode = NAND_ECC_HW;
+ nand-ecc.size = CONFIG_NAND_DENALI_ECC_SIZE;
+ nand-ecc.read_oob = denali_read_oob;
+ nand-ecc.write_oob = denali_write_oob;
+ nand-ecc.read_page =
Hi Charles,
I hit error when trying to apply the patch
bash-3.2$ git apply signing.patch
fatal: corrupt patch at line 205
On Thu, 2014-02-27 at 16:49 +1300, Charles Manning wrote:
Like many platforms, the Altera socfpga platform requires that the
preloader be signed in a certain way or the
Hi Scott,
On Thu, 2014-02-27 at 16:32 -0600, Scott Wood wrote:
On Thu, 2014-02-27 at 15:02 -0600, Chin Liang See wrote:
Hi Masahiro,
On Thu, 2014-02-27 at 23:35 +0900, Masahiro Yamada wrote:
Hello Chin,
+
+ nand-ecc.mode = NAND_ECC_HW;
+ nand-ecc.size
Hi Michal,
On Fri, 2014-02-28 at 11:17 +0100, Michal Simek wrote:
On 02/27/2014 05:03 PM, Chin Liang See wrote:
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See cl...@altera.com
Cc
On Fri, 2014-02-28 at 11:30 +0100, Michal Simek wrote:
On 02/27/2014 08:53 PM, Chin Liang See wrote:
To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file within include/configs folder.
Signed
On Fri, 2014-02-28 at 11:31 +0100, Michal Simek wrote:
On 02/27/2014 08:55 PM, Chin Liang See wrote:
Hi Michal,
On Mon, 2014-02-24 at 08:52 +0100, Michal Simek wrote:
On 02/21/2014 09:57 PM, Chin Liang See wrote:
To enable the DesignWare watchdog support at SOCFPGA Cyclone V
dev kit
On Fri, 2014-02-28 at 11:37 +0100, Michal Simek wrote:
+/* lld_nand.h */
+/*
+ * NAND Flash Controller Device Driver
+ * Copyright (c) 2009, Intel Corporation and its suppliers.
+ *
+ * This program is free software; you can redistribute it and/or modify
it
+ * under the terms and
Hi Masahiro,
On Fri, 2014-02-28 at 21:57 +0900, Masahiro Yamada wrote:
Hello Chin,
Where do you set nand-ecc.strength?
I believe this is only applicable for NAND_ECC_HW_SYNDROME mode. We are
using the NAND_ECC_HW (without the syndrome). Wonder you hit error
during run?
To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file within include/configs folder.
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Anatolij Gustschin ag...@denx.de
Cc: Albert Aribaud albert.u.b
Clock Manager driver will be called to reconfigure all the
clocks setting based on user input. The input are passed to
Preloader through handoff files
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc: Wolfgang Denk w
Hi Pavel,
Hi!
Clock Manager driver will be called to reconfigure all the clocks
setting based on user input. The input are passed to Preloader through
handoff files
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Albert Aribaud albert.u.b...@aribaud.net
Cc: Tom Rini tr...@ti.com
Cc
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Tom Rini tr...@ti.com
Cc
Hi Pavel,
On Mon, 2014-03-03 at 21:41 +0100, ZY - pavel wrote:
Hi!
Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See cl...@altera.com
Cc: Dinh Nguyen dingu...@altera.com
Cc
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