On 08/09/2017 02:18 PM, Marcel Ziswiler wrote:
On Wed, 2017-08-09 at 12:51 -0600, Stephen Warren wrote:
On 08/09/2017 09:44 AM, Marcel Ziswiler wrote:
From: Marcel Ziswiler
Allow optionally bringing up the Apalis type specific 4 lane PCIe
port
as well as the PCIe switch as found on the Apalis
On Wed, 2017-08-09 at 12:51 -0600, Stephen Warren wrote:
> On 08/09/2017 09:44 AM, Marcel Ziswiler wrote:
> > From: Marcel Ziswiler
> >
> > Allow optionally bringing up the Apalis type specific 4 lane PCIe
> > port
> > as well as the PCIe switch as found on the Apalis Evaluation board.
> > In
> >
On 08/09/2017 09:44 AM, Marcel Ziswiler wrote:
From: Marcel Ziswiler
Allow optionally bringing up the Apalis type specific 4 lane PCIe port
as well as the PCIe switch as found on the Apalis Evaluation board. In
order to avoid violating the PCIe reset timing do this by overriding the
tegra_pcie_
From: Marcel Ziswiler
Allow optionally bringing up the Apalis type specific 4 lane PCIe port
as well as the PCIe switch as found on the Apalis Evaluation board. In
order to avoid violating the PCIe reset timing do this by overriding the
tegra_pcie_board_port_reset() function. Note however that bo
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