Re: [USRP-users] Random errors while transmitting certain BPSK/QPSK types on x310s

On 07/06/2017 09:36 PM, Michael Carosino via USRP-users wrote: A quick update to this question with more info. I did some further analysis by capturing the received I/Q data from the USRP Source block when transmitting the BPSK that works without errors (symbols are 0.707+0.707j,

Re: [USRP-users] Random errors while transmitting certain BPSK/QPSK types on x310s

A quick update to this question with more info. I did some further analysis by capturing the received I/Q data from the USRP Source block when transmitting the BPSK that works without errors (symbols are 0.707+0.707j, -0.707-0.707j) and also when using the BPSK that gives errors (symbols are

[USRP-users] Random errors while transmitting certain BPSK/QPSK types on x310s

Hi all, running Gnuradio 3.7.10.2 and UHD 4.0.0 rfnoc-devel latest commit (tried earlier versions too). I've got a simple tx/rx flowgraph going on. The simple description is: Random input data -> Pack 1 Bit->Chunks to Symbols->Interpolating FIR Filter->USRP Sink USRP Source-> Polyphase Clock

Re: [USRP-users] USRP N-series loading FPGA

Hello Daniel, No, the storage is non-volatile. The script only needs to be run when updating the FPGA. Regards, Derek On Thu, Jul 6, 2017 at 9:40 PM, Cho, Daniel J (332C) via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello – > > > > In order to load a custom FPGA, you run the python

[USRP-users] USRP N-series loading FPGA

Hello - In order to load a custom FPGA, you run the python script "uhd_image_loader --args="type=usrp2,addr=" --fw-path="" --fpga-path=""" which is then automatically loaded at runtime. Is that on-board storage volatile? Will I have to run this python script every time I reboot the USRP

Re: [USRP-users] USRP Device based upon highest rate capability

Daniel, all of our devices are listed (with rates) on our website: https://www.ettus.com/product The X-series has the highest achievable rates. What you can sustain depends on many things, including the computer running UHD and the implementation. An E-Series typically won't be able to sustain

Re: [USRP-users] Trigger Signal

Mareike, the reason for the delays is that your software is polling the GPIO, and that goes over network. You're adding in network latency, and SW scheduling latency. Also, with the DDC, once a packet leaves the computer, it needs to go through various stages before it reaches the ADC (after the

Re: [USRP-users] B210 on VirtualBox VM - USB settings

I meant to add that you will also still need to set the udev rules in the VM too (I'm assuming that you're using Ubuntu 16.04 as the guest OS). https://files.ettus.com/manual/page_transport.html#transport_usb_udev --​Neel Pandeya On 6 July 2017 at 11:51, Neel Pandeya

[USRP-users] rfnocmodtool test bench

Hi, I am trying to test a custom block built using rfnocmodtool and I get this error when I run make noc_block__tb *Setting up a 64-bit FPGA build environment for the USRP-X3x0...* *- Vivado: Found (/opt/Xilinx/Vivado/2015.4/bin)* *- Vivado HLS: Found (/opt/Xilinx/Vivado_HLS/2015.4/bin)*

Re: [USRP-users] How to Compile rx_samples_to_file and Generate an Executable

Hi Altug and Jacob, Yes, the most recent Visual Studio we are actively supporting is 2015. We will support 2017 with an upcoming release but as you note Jacob, Boost and other dependencies are still catching up themselves. Jacob, Boost 1.64 is not officially supported but great to hear it is