On 08/10/2018 07:47 PM, Mark Wagner via USRP-users wrote:
Hi USRP mailing list,
I'm having trouble installing UHD from source. I've been following the
instructions on this page
https://kb.ettus.com/Building_and_Installing_the_USRP_Open-Source_Toolchain_(UHD_and_GNU_Radio)_on_Linux
On 08/10/2018 10:57 PM, Samuel Prager wrote:
Hi Marcus,
Thanks for the response. Say I am simply receiving samples and not
doing anything with them — just overwriting a buffer. Can you tell me
what is the approximate maximum rate of the AXI interface?
Thank you,
Sam
I don't have an exact
Hi USRP mailing list,
I'm having trouble installing UHD from source. I've been following the
instructions on this page
https://kb.ettus.com/Building_and_Installing_the_USRP_Open-Source_Toolchain_(UHD_and_GNU_Radio)_on_Linux
but I keep running into the same problem. I've cloned the latest
On Fri, Aug 10, 2018 at 5:03 PM Anton Schlegel via USRP-users <
usrp-users@lists.ettus.com> wrote:
> I am having trouble setting up the transmission chain with RFNOC on an
> X310. I was able to transmit and receive using multi_usrp on B205.
>
> For transmission, I understand that the RFNOC
I am having trouble setting up the transmission chain with RFNOC on an
X310. I was able to transmit and receive using multi_usrp on B205.
For transmission, I understand that the RFNOC process will be
DmaFIFO->DUC->Radio. Then I can create a tx_streamer and transmit the
needed information.
When
Hi Marcus,
with UHD 3.10 we could run GR flowgraphs for hours. It recognizes the
daughterboardand everything.
I hope R can help.
Cheers
Johannes
Von: USRP-users im Auftrag von Marcus D.
Leech via USRP-users
Gesendet: Freitag, 10. August 2018 18:28
An:
On 08/10/2018 12:45 PM, Samuel Prager via USRP-users wrote:
Hello,
I have been unable to find answer as to what is the maximum streaming
data rate is from the zynq fpga to the arm processor in the N3xx USRPs
operating in embedded mode.
Does anyone have an answer to this question?
Thank
Hello,
I have been unable to find answer as to what is the maximum streaming data rate
is from the zynq fpga to the arm processor in the N3xx USRPs operating in
embedded mode.
Does anyone have an answer to this question?
Thank you,
Sam
Samuel Prager
PhD Student, Electrical Engineering
I experianced the same issues that EJ mentioned last year (maybe earlier). At
the time Jon, helped me with a patch to get it to work properly (this was an
OOT that sent out a specific chunk of samples on repeat [I think I mentioned
this in a thread a few weeks ago]). I am not sure if it is
Hi Koen,
There's also a potential deadlock situation to watch out for: If your block
output samples to the axi_wrapper *before* UHD software assigns a
destination address, I've seen the axi_wrapper FIFO become full and
deadlock somewhere in the transmit path. This was an issue several 6-12
months
Hi Carry,
Unless you left out some more details, it sounds like you just want to
transmit. In that case you should use the regular UHD API and you can
ignore my previous suggestions. Take a look at the examples
tx_waveforms.cpp and tx_samples_from_file.cpp for how to use the UHD API.
Jonathon
Hi Koen,
Your block should not wait on tready, that is a violation of the AXI spec.
Some blocks actually wait for tvalid to be asserted before asserting tready
(that is permitted by the spec), which would cause a deadlock in your
situation. You can work around that by putting an axi_flip_flop in
Thanks Jonathon!
I want to send some data block to radio. I need to use uhd on arm and send the
data. now I want to put the data block on ps memory, and access the data block
in pl, so I can send the data block in PL direct!
can I setup my own datamover on another HP AXI port under uhd fpga
Hello all,
Last week I posted a question, on how I could confirm that a custom RFNoC
signal generator (piloted from a UHD API) functioned as intended. I received
the tip to probe my block using the Vivado ILA. A great idea, because I did not
know this existed (I am quite new in FPGA design)
Hi Marcus,
I put my answer on top. I hope that doesn't lead to confusion.
Regarding (A): I hope it should work. How would I proceed to debug it?
Regarding (B): We have a laptop with a 1G NIC, a 1G switch and a USRP2
on the other end.
This setup works with UHD3.10 (see my initial email on the
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