Thanks EJ and Nick,
I hadn't thought about the propagation of the streaming command occurring
in UHD rather than on the FPGA. I was thinking that after issuing the
rx_streaming start command to the downstream-most block in the chain, some
magic was happening on the FPGA to get the upstream blocks
Thanks Jonathon!
On Thu, Mar 28, 2019 at 5:24 AM Jonathon Pendlum
wrote:
> Hey Rob,
>
> Regarding overflows or dropped packets, is this something that might
>> occur inside the FPGA (CE to CE) or is it just a concern on the
>> transfer to the host CPU (which is my only experience with overflows
On 03/28/2019 07:26 AM, Nicolas GALLAND wrote:
Hi,
I used the file named usrp_x310_fpga_HG.bit
Nicolas
Could you show me an ifconfig for the interface that you're using for
the device?
Le 27/03/2019 à 15:10, Marcus D. Leech a écrit :
On 03/27/2019 05:39 AM, Nicolas GALLAND wrote:
Hi,
And you have a 1Gb SFP plugged into the first port in the X310 going to a 1GB
connection on the other end?
From: USRP-users on behalf of Nicolas
GALLAND via USRP-users
Sent: Thursday, March 28, 2019 7:26 AM
To: Marcus D. Leech; Joe Martin
Cc:
Michael, thank you. That does help.
Do you or anyone know if there is a version of Ubuntu or Debian [or
any distro] that supports the default PyBombs installation out of the
box? I don't have time to learn pybombs and debug the build.
Thanks,
Martin Klingensmith
On Wed, Mar 27, 2019 at 2:56 PM
Hi,
I used the file named usrp_x310_fpga_HG.bit
Nicolas
Le 27/03/2019 à 15:10, Marcus D. Leech a écrit :
On 03/27/2019 05:39 AM, Nicolas GALLAND wrote:
Hi,
after the recovery, i can't ping the device to the default address.
It gives me a "host unreachable" error when I try.
Nicolas
Hello Ian,
I want a continuous TX of a generated signal, because I want to use the USB
exclusively for RX. I don't know if I can configure by UHD this option at first
time, without sending data all time and modifying the input TX data of the
b205_io block with my desired signal. Is this
Hey Rob,
Regarding overflows or dropped packets, is this something that might
> occur inside the FPGA (CE to CE) or is it just a concern on the
> transfer to the host CPU (which is my only experience with overflows
> or dropped packets)? If on the FPGA, what would be the cause of
> overflows /
Hello,
I am trying to mex the file multi_usrp.hpp located on my
computer in the folder:
C:\Program Files\UHD\include\uhd\usrp\multi_usrp.hpp
However i get the error:
multi_usrp.hpp : fatal error LNK1107: invalid or corrupt file:
cannot read at 0x105AE
