Yes, I've used it, no custom block controller required. Attached are XML
and GRC descriptors.
On Sat, Sep 7, 2019 at 11:22 AM d.des wrote:
> I wonder if you have successfully used this block with grc or if you
> were just using it with uhd. When I try to use the 2-input, 1-output
> block in grc
Thanks Michael,
This info was very helpful.
Regarding "recv_buff_size", I tried setting to 100M and received a warning
that it could not do so because rmem_max was only 33M. Given that my
rmem_max was set all along to 33M, would the recv_buff_size default to 33M
or does it default to something
Hi Rob,
I would recommend not using the DMA FIFO block. Although the DMA FIFO
block should work, setting a larger socket buffer on the host or using DPDK
are much better options. To use a larger socket buffer, just use the
device argument "recv_buff_size=" and set the to something
reasonably
Hi Nate,
I looked at the link you sent (performance tuning tips) and your email.
Here are a few comments / questions:
- Regarding my initial question, what could be the cause of WORSE
performance when I inserted the DmaFIFO in the receive chain of my RFNoC
graph? Recall the
Hi,
I am having trouble running the FFT block of size 1024 on an N310. I am
using the "rfnoc_rx_to_file" example program (UHD v3.14.1.0) to run it. It
works with size 256 or 512. Additionally, I am able to run with 1024 if I
switch to an X310 (same PC). Please let me know if you have any
Hey,
sorry to post again, but I think this time I have a solution.
In my grc-generated python file I added the lines:
cmd_time_1 = self.sender_A.get_time_now() + uhd.time_spec_t(5.0)
self.uhd_rfnoc_streamer_fifo_0_0.set_start_time(cmd_time_1)
Hi Sam,
Thanks for your kind words.
Firstly, it had detection problems. Even, after writing FPGA image nothing
happened. There were no indications, that it failed. I assumed it is dead,
since after successful image writing, nothing happened. I waited for
sometime, maybe after I wrote email, I