Re: [USRP-users] ADC + DAC Compare of N200 and B200

Hello Kevin, No, the N200 and B200 do not change the electrical transport modes based on the frequency or bandwidth requested by the application, there is no need. The 12 and 14 digital bits are available at all frequencies. The actual effective number of bits out to the host depends on the ADC

Re: [USRP-users] uhd_usrp message return and Comms issues

Hi Mark, I'm glad to hear you were able to update to 3.9. Retuning the UBX takes approximately 500 usec. This varies based on how far the internal VCO needs to tune and if there is a band crossing. A dwell time of 5 seconds (5,000 msec) should be four orders of magnitude more than is needed to

Re: [USRP-users] warning on UDP buffer size when using Python API

Hello, The requested sizes do change a little during the initialization. Also the settings are not persistent across reboots of your host computer so need to be re-appled each time you restart or changes made to other configuration files to make them persistent. Can you confirm which sizes you

Re: [USRP-users] uhd_usrp message return and Comms issues

Hello Mark, It has been some time since I have looked at the probe routine in the 3.8 version of UHD, but it sounds like the discovery packets are having routing problems. Do you have an N210, N200, or USRP2 anywhere on the network? We can probably give some assistance to discovering the root

Re: [USRP-users] Advise on how to modifying HDL design E310 to add custom blocks

Hello Brais, The HDL design does have a top block and is composed of usefully divided sub blocks. It is not however designed using the graphical Vivado workflow, but a source based one. Here is the top block: https://github.com/EttusResearch/fpga/blob/maint/usrp3/top/e300/e310.v Your application

Re: [USRP-users] the rfnoc fifos

Hi Jason, Adding FIFOs adds buffering which helps with any transient changes in throughput, such as over the 10 GigE connection. It gives the flow control more room to work with before an overflow occurs (on receive). On the transmit side the DMA FIFO usually fills that role. On Fri, Sep 29,

Re: [USRP-users] X300 STREAM_MODE_NUM_SAMPS_AND_DONE length limitation

That assertion is protecting a register in the Radio Block on the FPGA. You could try modifying that area of the logic which is counting the outputted samples as they are packetized. I do not believe that other areas of the code would be impacted (other than that assertion in the host code of

Re: [USRP-users] 4 Rx channels from an X310

Hello Joshua, The default FPGA image now has two DDCs which each have two DSP chains. The message you link to is from 2014 and we've substantially updated the contents of the FPGA since then. Currently the TwinRX is the primary daughtercard making use of these additional DDC chains as the others

Re: [USRP-users] uhd_rx_nogui gets really noisy!

Hello Ali, You have not set a gain value in your command. You can check the GRC example to find the default gain or try values until you see a strong signal. Regards, Derek On Sat, Sep 9, 2017 at 9:59 AM, Ali The GREAT! via USRP-users < usrp-users@lists.ettus.com> wrote: > Dear all, > > I

Re: [USRP-users] How to use RFNoC framework with LFRX daughter board?

Hello, Can you please paste a copy of the full output, including the command, for uhd_usrp_probe? That will include a lot of information which we can use to offer advice. Thanks, Derek On Wed, Aug 30, 2017 at 11:21 AM, L TP via USRP-users < usrp-users@lists.ettus.com> wrote: > > Hi List, > I'm

Re: [USRP-users] Support with setting usrp sampling rate to 150MSPS

Hello Koyel, This is a fundamental problem that increasing sample rate takes more processing power to handle but provides more bandwidth of spectrum. How wide is the signal you need to process? The general recommendation is that you sample at 1.25 times your bandwidth. This provides 20% more

Re: [USRP-users] Support with setting usrp sampling rate to 150MSPS

Try 200MS/s. The FPGA can only decimate integer amounts from the ADC rate, which is 200MS/s. On Tue, Aug 22, 2017 at 5:15 PM, Snehasish Kar via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello > I am trying to receive gsm 1800 band using NI USRP 2954R, but when I am > trying to set the

Re: [USRP-users] Receiver Sensitivity of NI USRP 2954R

Hello Snehasish, Here is the performance data for the UBX daughtercard and X3x0. The sensitivity changes with frequency and gain. http://files.ettus.com/performance_data/ubx/UBX-without-UHD-corrections.pdf Regards, Derek On Wed, Aug 16, 2017 at 8:14 AM, Snehasish Kar via USRP-users <

Re: [USRP-users] UHD Version for New UBX Hardware Rev

Hello Dave, This commit added the EEPROM IDs for the updated UBX version. https://github.com/EttusResearch/uhd/commit/f5a082fd3841571d2a53a9e677b5dfe6d653bd94 It was added August 22nd and 3.9.5 has it. I believe there have been a few improvement changes since then which are on the 3.9 branch,

Re: [USRP-users] Multiple RX channels on X310

Hello Daniele, If you run uhd_usrp_probe you will see a list of the supported frontends. The example is for the TVRX2 daughterboard which you are probably not using. The most common subdev specifications for a single X310 are "A:0 B:0" (First channel of each daughtercard) and "A:0 A:1 B:0 B:1"

Re: [USRP-users] Problems receiving valid data from a multi_usrp

If you do not need any time synchronization then you can use four separate rx_streamers. The time source (and clock source) will default to internal. Do you have MIMO cables between the N210s? Given that you have four that won't save you from having to have a separate external 10 MHz and PPS to

Re: [USRP-users] Problems receiving valid data from a multi_usrp

Hi Janos, The problem is that the single rx_streamer is trying to time align the samples from the four USRPs, but the onboard clocks are not aligned so it is not finding samples from the same moment. Are you sharing 10 MHz and 1PPS references to all the USRPs? If so you will need to set the clock

Re: [USRP-users] XCVR2450 with X310

Hello Jon, As you have found in the documentation and see in the output of uhd_usrp_probe, the XCVR2450 is not supported on the X3x0 family. We are sorry this is true, but we do not have any current timeline for adding this support nor do we have any advice right now to give for what changes

Re: [USRP-users] When ssh'ing Getting prompt for Password Issue

Hello, Yes, a micro SD card adapter is needed. I'm going to add to our documentation to highlight that point. There is no way to overwrite the entire SD remotely. This is true for nearly every embedded system. We do not have any recommended micro SD card adapter. There are many from good brands

Re: [USRP-users] PPS and REF out form a X310 and leakage problem

Hello Jorge, The Octoclock is sold in two versions, one with an internal GPSDO and one that requires an external source. The X310 and X300 both do not support daisy chaining. There are a few issues with it, one of the key ones being propagation delay. If the 1PPS signal was passed from one unit

Re: [USRP-users] When ssh'ing Getting prompt for Password Issue

Hi Konstantin, We have no way of knowing what device the SD Card will enumerate as. There are many guides online for using utilities like fdisk and dmesg to find the name of the device. Using Windows or Linux you will need to remove the micro SD card and use a USB to micro SD card adapter to

Re: [USRP-users] When ssh'ing Getting prompt for Password Issue

Hello Konstantin, The download definitely works on Windows, Mac, and Linux so there must be some issue with your VM that is causing the issue. That is probably beyond what we can help with. On Windows you can use 7zip to extract the xz archive and win32diskimager for writing the filesystem image

Re: [USRP-users] Support with UHD C++ API

Hello Snehasish, The UHD examples contain all the code to receive a stream of samples at that rate. What have you tried? We may be able to help better if you explain what is not working. 50 MS/s is not too high of a load so most recent computers should have no problem receiving that much data

Re: [USRP-users] Trying to verify Rx MIMO operation of x310

Hi Mark, I've added back on the list, it's useful to keep everyone in sync with progress. The WX FFT only takes one input but the QT Frequency Sync has a configurable number of inputs. In general the QT GUIs are being promoted over WX. Regards, Derek On Tue, Aug 1, 2017 at 7:40 PM, Mark

Re: [USRP-users] PPS sync with USRP E310 timeout error

Hello Daniel, There is no check in your code to confirm that the time is correctly set. The 1PPS signal should be a square wave rather than a sine wave. It is a logic signal rather than an RF one and the sync port is designed to handle it.

Re: [USRP-users] One USRP device is not connected to the host computer

Hi Adhitha, I'm glad that's worked for you. Best regards, Derek On Tue, Aug 1, 2017 at 4:19 PM, Adhitha Dias wrote: > Hi Derek, > > I tried with the large netmask. Now it's working. Thank you so much for > the help. Really appreciate it! > > I am using UHD version

Re: [USRP-users] Trying to verify Rx MIMO operation of x310

Hi Mark, Unfortunately you're up against the limits of the included examples. There are no UHD only examples which store multiple channels of samples to a file. The rx_multi_samples shows the steps involved in setting up the channels, but doesn't implement the functionality shown in

Re: [USRP-users] One USRP device is not connected to the host computer

Hello Adhitha, If you are connecting only one USRP at a time directly to the computer and see one work and one not then my first guess would be that the IP address has changed on the second one. Try running uhd_find_devices, this will work if the IP address is different but still on the same

Re: [USRP-users] Trying to verify Rx MIMO operation of x310

Hello Mark, rx_samples_to_file will only receive a single channel. It is a minimal example. Try: rx_multi_samples --channels 0,1 This will receive two channels, a pair of UBXs only has one RX channel per daughterboard so UHD can infer the sub device specification. The default sample rate is 100

Re: [USRP-users] Windows driver for B210

Hello Anuja, That zip contains the USB driver for the B210, it is the same as the B200. If you encounter an error message then unplug and replug the B210. This is a non-fatal error that is seen occasionally with different Windows versions. Regards, Derek On Mon, Jul 31, 2017 at 11:54 AM, Anuja

Re: [USRP-users] TwinRX + X300 Usage

Hello Christian, Your configuration of the LO sharing is all reasonable. You are not using timed commands so you will not get repeatable phase offsets between the channels due to the DDC's CORDIC and the RX frontend's IF downconverter not being synchronously reset. The call to set_rx_freq for

Re: [USRP-users] Disabling CORDIC

Hello Altug, If you tune using the tune request with a DSP policy of MANUAL and DSP frequency of 0.0 then yes, that channel's CORDIC will not alter the samples. A policy of NONE will leave the DSP in the last configured state, so it is better to be explicit. Regards, Derek On Wed, Jul 26,

Re: [USRP-users] 答复: frequency shift of B210

Hi Jong, Marcus Leech and Marco have both offered good advice on testing the frequency stability of the B210 against outside references. Have you tried either? Marcus Muller also asked for additional information about your test setup. Regards, Derek On Wed, Jul 26, 2017 at 2:04 AM, john liu

Re: [USRP-users] Using a reference clock on USRP E310/312

Hello, To get time and frequency alignment on a pair of E31xs you can supply the 1PPS to both units. The example programs do not all support setting the time source. http://files.ettus.com/manual/page_usrp_e3x0.html#e3x0_hw_sync Here is an example which supports setting the time source, you can

[USRP-users] 3.10.2.0 Release Candidate 1 Announcement

Hello all, The release candidate of UHD version 3.10.2.0 has been tagged and is available for testing. There have been no API breaking changes necessary since the last release but a small ABI change means we are incrementing the ABI number. Updated FPGA and firmware images have been uploaded.

Re: [USRP-users] DDC's Filters in B210

Hello Altug, The CIC can be programed to decimate by a range of integer amounts. If the ratio is 20 (50 MHz sampling rate, 2.5 MHz output rate) then both half bands will be used (divide by 2*2) and the CIC will decimate by 5. Odd CIC rates have poor filter roll off compared to even rates. Derek

[USRP-users] 3.9.7 Release Announcement

Hello all, The 3.9.7 release of UHD has been posted. This is an update to the Long Term Support series. There was one commit between the release candidate and the final release. This added some safety checks to the uhd_images_downloader script when using custom destination directories. The tag

Re: [USRP-users] TwinRx not recieving waveform

Hi Bradon, The TwinRX should show up as a TwinRX in the RX slot and an unknown daughterboard in the TX slot. This is a cosmetic issue which we're aware of. It is possible that you have a revision B TwinRX which has a newer ID than is supported by your version of UHD. Can you please post the full

Re: [USRP-users] TwinRx not recieving waveform

Hello Brandon, How did you install UHD and GNU Radio? When you say that the USRP is not receiving the waveform, do you see just noise or does the application not even start? What file was missing, there should definitely not be anything missing from those versions. I recommend ensuring that

Re: [USRP-users] Removing the whole LO signal when transmitting

Hello Brais, The gain values for USRPs are indexed from 0 dB gain being minimum gain up to the device's maximum. Usually this means that 0 dB of gain is actually a large amount of attenuation or loss through the RX chain. The same is true for TX. It doesn't surprise me that you are seeing those

[USRP-users] 3.9.7 LTS Release Candidate 1 Announcement

Hello all, The release candidate of UHD version 3.9.7 has been tagged and is available for testing. This is an update to the Long Term Support series and is planned to be released next Monday, the 17th. The tag for this release candidate:

Re: [USRP-users] USRP N-series loading FPGA

Hello Daniel, No, the storage is non-volatile. The script only needs to be run when updating the FPGA. Regards, Derek On Thu, Jul 6, 2017 at 9:40 PM, Cho, Daniel J (332C) via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello – > > > > In order to load a custom FPGA, you run the python

Re: [USRP-users] How to Compile rx_samples_to_file and Generate an Executable

Hi Altug and Jacob, Yes, the most recent Visual Studio we are actively supporting is 2015. We will support 2017 with an upcoming release but as you note Jacob, Boost and other dependencies are still catching up themselves. Jacob, Boost 1.64 is not officially supported but great to hear it is

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