Re: [USRP-users] Latency between multiple daughter boards on one USRP X310

2018-07-31 Thread Young C. Park via USRP-users
Fabian and Derek, Thanks for your comments, Yesterday I realized that 10GbE could not support my 100MSymps, complex dual channel output. That's why I've seen underflow messages. I actually have got around this underflow by putting (ms) delay between bursts. However, it seems like that there's

Re: [USRP-users] Latency between multiple daughter boards on one USRP X310

2018-07-30 Thread Derek Kozel via USRP-users
Hello Fabian and Young, The suggestion about timed commands is on point, I think that is what is missing. Using unknown PPS will not hurt as there are two radio blocks with timekeepers and using the unknown PPS setting, or external or gpsdo if installed, will ensure that they are aligned. > 3)

Re: [USRP-users] Latency between multiple daughter boards on one USRP X310

2018-07-30 Thread Fabian Schwartau via USRP-users
Hi Young, I am not an expert, but I have three suggestions: 1) Using 'Unknown PSS' or any other sync method should not have no affect, as this is for syncing two or more USRPs. You have only one FPGA and that is in sync with itself ;) 2) Did you tried using timed commands? (see function

[USRP-users] Latency between multiple daughter boards on one USRP X310

2018-07-30 Thread YoungC_Park via USRP-users
Hi all, I hope someone could help me on my situation. I could not find similar cases on the usrp archive. I have one USRP X310 that has UBX-160(slot A) , LFTX board(slot B) and GPS module installed. - my UHD is 3.11.0 - Using uhd API based on tx_samples from_file.cpp, I can generate dual