Ian,
It turns out the B210s were not phase aligned (contrary to my earlier
report)- we had not done our measurements correctly. So, need to get the
MCS proof-of-concept working on two B210s i.e. just prove on the scope that
the baseband RX sample clocks are indeed aligned. Currently we call a uhd
Ian,
We are using multiple B210 radios. We are monitoring two PPS signal (one
per radio) reclocked in the radio/sample clk domain on the scope. So
essentially, we are indirectly monitoring the radio clk/sample clk from two
different B210s, which always seem phase aligned over multiple reboots.
Bu
Chintan,
When you refer to lab trial’s with B210…I’m assuming you were using multiple
B210’s rather than demonstrating coherence of the 2 channels on a singe B210?
How were you verifying that the sample clocks were aligned? Can you share your
rough configuration?
If you are using a common PPS to
Hi Ian, Robin, Marcus
Thanks a lot for your help so far. Three more questions/clarifications:
1. For the B205 Multi-chip sync (MCS), we are trying to achieve, we are
actually providing an external stable 40MHz clock common to both B205s.
i.e. we have re-worked the boards so that the DPLL is not b
Ian is correct regarding B210 and B200mini not supporting an external LO.
It is worth noting that we do support external LO mode for the N310 (the
AD9371 has the same divide-by-2 as the AD9361) and optionally for the N230.
In any event, the ADI Engineer Zone post in my original message references
Robin,
that ADI support thread is not applicable to B2x0, it’s for AD9361 external LO
mode which isn’t used by Ettus products.
In internal LO mode there is always a phase ambiguity in the RF synthesizers
that requires higher level S/W to calibrate and correct for.
The baseband synthesizer can b
Marcus is correct and the schematics do in fact provide the answer.
Please refer to p.1 of the B210 schematic. It contains an ADF4002 analog
PLL.
The B200mini clocking circuitry is on p. 4 of the schematic. The PLL is
digital and implemented inside the FPGA.
There is a divide-by-2 for the exter
On 06/25/2018 11:57 PM, Dan CaJacob wrote:
Without looking at the schematic, I'd guess that the difference is in
the implementation of the PLLs for tracking.
On Mon, Jun 25, 2018 at 11:21 AM Chintan Patel via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hi Marcus,
Two follo
Without looking at the schematic, I'd guess that the difference is in the
implementation of the PLLs for tracking.
On Mon, Jun 25, 2018 at 11:21 AM Chintan Patel via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi Marcus,
>
> Two follow-up questions related to B205/B210 synchronization.
>
>
Hi Marcus,
Two follow-up questions related to B205/B210 synchronization.
1. What is the fundamental reason why B210 supports phase coherent sync
across multiple devices and B205 does not. The reference manuals on the
AD9364/AD9361 does not point to any clues, and neither does the schematic.
2.
On 06/23/2018 09:06 AM, Chintan Patel wrote:
Hi Marcus,
Thanks for the response. I came to a similar conclusion reading the
Ettus app note on MIMO synchronization.
Do you know if the DPLL code (or any other way) can be modified to
achieve phase coherence across multiple B205 minis.
My unders
On 06/23/2018 12:25 AM, Chintan Patel via USRP-users wrote:
Hello,
I am an Ettus newbie. We have an application that requires us to
synchronize multiple B205 mini radios (RX side) using the PPS in
signal. In the FPGA, the pps_in is reclocked into the radio clock
domain. What we notice is that
Hello,
I am an Ettus newbie. We have an application that requires us to
synchronize multiple B205 mini radios (RX side) using the PPS in signal. In
the FPGA, the pps_in is reclocked into the radio clock domain. What we
notice is that when we monitor this PPS signal (reclocked in radio clock
domain
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