Hello everyone,
I have a problem with OFDM frame detection for one of my channels. I work
with gr-ieee802-11 blocks and receive from 4 channels using X300 and 2
TwinRX. For the frame detection, the receive blocks calculate the
autocorrelation of the incoming stream over a specified window size and
I have generally had to use external power with Odroids for B2xx.
Sent from my iPhone
> On Feb 17, 2018, at 8:02 AM, Marcus Müller via USRP-users
> wrote:
>
> Hi Roman,
>
> sorry for the delay in getting back to you:
>
> Regarding the power consumption: I
Ooh, I forgot about the FPGA vs analog side. Thanks gents!
On Sat, Feb 17, 2018 at 11:10 AM, Marcus Müller via USRP-users <
usrp-users@lists.ettus.com> wrote:
> To expand on that: timed commands do exist for all things that the FPGA
> can control – that is: start/stop of sampling, DSP
Hi Tim,
You used the wrong device. Burn to the device as whole, not to a
partition.
Best regards,
Marcus
On Wed, 2018-01-31 at 11:39 -0700, Tim Sapio via USRP-users wrote:
> Hello USRP-users,
>
> I have hit a snag uploading the images required to make my USRP2
> function. I will give a brief
Hi Sumit,
my first reaction would be to just merge the two flow graphs and do the
collision in software – 100% isolated from changing environments and
such.
From a hardware perspective: you can use the PPS input on the B210 to
set a synchronous time and then trigger transmitting on time stamps.
Hi Tarik,
that REF out port is the 10 MHz clock, and you can choose the internal
GPSDO as clock source[1]. Same goes for the PPS out port.
Theoretically, you could "daisy-chain" your USRPs, but I wouldn't
generally recommend that (we haven't characterized delay, and also, if
you can, always avoid
Snehasish,
no.
Best regards,
Marcus
On Mon, 2018-02-12 at 11:03 +, Snehasish Kar via USRP-users wrote:
> Hello
>
> Is it somehow possible to add more than 10 gnu-radio blocks in
> uhd_image_builder.
>
> BR
> Snehasish
>
> ___
> USRP-users
Dear Xingjian,
that won't be possible as is – the tuning happens in the AD9361, and
the FPGA communicates with that over a serial link. There's timing
accuracy requirements that we can't meet over that serial link, so
that's why Ettus' AD936x-based device can't support timed commands on
the
Hi Kasper,
SIMD is fine and all, for sample processing in the end (for example, to
convert the samples from on-the-wire format to something your CPU can
calculate with), but it's really no "fix it all" for this kind of
thing:
Significant workload is handling the fact that your USB controller has