[USRP-users] Updated BSP for e3xx

2018-04-16 Thread Kurt Kiefer via USRP-users
The last release of the BSP and firmware for e3xx devices is either back at fido, which was over two years ago, or jethro a year ago (though it's still listed as "beta" on files.ettus.com). This age makes it increasingly difficult to find compatible tooling without performing complicated manual

Re: [USRP-users] boost 1.67.0 compatibility issues with GR and UHD

2018-04-16 Thread Martin Braun via USRP-users
On 04/16/2018 10:09 AM, Michael Dickens via USRP-users wrote: > Boost 1.67.0 was released over the weekend, and there are > incompatibilities introduced by it for both GNU Radio and UHD -- both > release and current GIT master of each. Volk latest release as well > as current GIT master both seem t

Re: [USRP-users] RFNoC support for maint branch

2018-04-16 Thread Derek Kozel via USRP-users
Hello Leo, You are correct, use of custom RFNoC blocks is only supported on the rfnoc-devel branch at this time. The full RFNoC support will be exposed on the main branches in the future, the UHF 4.0.0.0 release is the currently planned time for doing that. Regards, Derek On Wed, Apr 11, 2018 at

[USRP-users] boost 1.67.0 compatibility issues with GR and UHD

2018-04-16 Thread Michael Dickens via USRP-users
Boost 1.67.0 was released over the weekend, and there are incompatibilities introduced by it for both GNU Radio and UHD -- both release and current GIT master of each. Volk latest release as well as current GIT master both seem to build and test cleanly using this new Boost version. The OS-inde

[USRP-users] [RFNOC] Schimdl & Cox off-the-shelf block fails timing constraints on X310

2018-04-16 Thread Francesco Restuccia via USRP-users
Hi all, I am trying to add the schmidlcox, fft and and eq to my X310. Looks like the S&C block does not meet timing constraints. This is the report from Vivado. Any help would be much appreciated, thank you... Francesco ---

[USRP-users] USRP B210 API & FPGA

2018-04-16 Thread Yeo Jin Kuang Alvin (IA) via USRP-users
Hi all, I have two questions regarding the USRP B210 configurations using API and FPGA at the same time. 1) USRP FPGA Source Code: I have used the Xilinx DDS Compiler using the Coregen and generated out a chirp signal using 2 phase accumulator followed by a SIN_LUT. However, I don't know