Hi all, I have two questions regarding the USRP B210 configurations using API and FPGA at the same time.
1) USRP FPGA Source Code: I have used the Xilinx DDS Compiler using the Coregen and generated out a chirp signal using 2 phase accumulator followed by a SIN_LUT. However, I don't know where to connect the 12 bits output at the SIN_LUT in the source code. Initially, I planned to connect directly to the tx_codec_d, but I noticed that tx_codec_d is connected to b200_io > b200_core > other modules. Can't seem to find a proper input at the Top module or anywhere that I can connect to. My current plan is to connect straight to tx_codec_d and comment off the connection that was previously connected to tx_codec_d in the source code, not sure if it works? 2) USRP API controlling AD9361: I am planning to control the AD9361 in the USRP B210 using the C++ source code given by ettus, located in uhd-maint/host/lib/usrp/common/. I am planning to build the ad9361_device.cpp & ad9361_ctrl.cpp & ad936x_manager.cpp to control the AD9361 to output my chirp signal generated by the FPGA code. Are the steps sufficient to achieve an output or are there more configurations that needs to be done? Hope someone can clarify my doubts and guide me along! Much appreciated! Thanks in advance!
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