May I ask what do you mean by host? Also, I can't remember but I read somewhere
before that any two input block is quiet buggy.
I was trying to locate the block controller script and xml script to modify it
and make it one output but couldn't locate the source yet.
I am running the Pybombs inst
That shouldn't be. Even if you connect both outputs to the host?
I admit I got fed up with it in my own application (don't want both streams
going into the host) and just modified the addsub block to be an add-only
block.
On Tue, Sep 3, 2019 at 8:43 PM Quadri,Adnan
wrote:
> I tried connecting o
I tried connecting one Signal Source block to both the inputs of addsub block.
It still throws the same error.
Adnan
From: Nick Foster
Sent: Tuesday, September 3, 2019 11:40:05 PM
To: Quadri,Adnan
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Addsub
Oh, I see. You have separate sources connected to the same addsub block.
It's telling you that you need to use timed stream commands to start the
stream, or else you will see undefined behavior. Personally I think that
error should be demoted to a warning -- anyone from Ettus want to chime in?
On
I ran into this the other day and it's independent of the HLS component of
the addsub block (since the interface is identical). You need to connect
both outputs of the addsub block to something, even a null sink. I'm pretty
sure this wasn't the intended behavior and also pretty sure that it wasn't
Hello,
We are trying to run the RFNoC addsub HLS block.
I was able to build the FPGA Image and made sure in the noc_block verilog code
to point to the HLS implementation for addsub block on RFNoC as opposed to the
verilog/VHDL implementation.
But when we run the example Flowgraph with two sign
On 8/20/19 7:40 AM, Jason Roehm via USRP-users wrote:
On 8/19/19 6:52 PM, Neel Pandeya wrote:
Hello Jason:
Thanks for all the detailed feedback! No worries about not having a
stand-alone reproducing program at the moment. Could you please try
using the head of the "UHD-3.14" branch? We
Hi everybody,
I experience a weird behavior while streaming from my N200 at low sampling
rates.
The setup is as follows: USRP N200 with latest FPGA image, UHD Version
3.14.1.0, Host computer is a Intel NUC Hades Canyon with Ubuntu 18.04 LTS and
CPU governor set to performance. The USRP is direc
Hi Sam,
Thank you for the information. Yes, you were right. I didn't see the LEDs
on the SFP port illuminating. I followed your instructions and the USRP
worked like a charm for all these days.
However, I didn't have any issues until yesterday. Yesterday, it suddenly
stopped working. I could see
