[USRP-users] Fw: a few questions on rfnoc

Hi, We are creating a RFNoC block that inputs a continuous flow of data and needs to output an irregular burst of variable length. I tried to research a bit but didn't found a final answer on the following questions: 1. Packets to and from RFNoC blocks need to have a min/max/fixed length?

Re: [USRP-users] Fw: a few questions on rfnoc

Hi Nicolas, Thank you very much for your quick response. Regarding variable packet sizes the output of my block is going straight to the host side and I am not planning these to connect to other blocks. In this case do you see any issue? Will uhd and gnuradio cope with that or will I have

Re: [USRP-users] RFNoC user registers and related APIs

uld easily include pre-RFNoC code (such as the radio core) into RFNoC. We do have a redesign of that bus on our RFNoC roadmap to make it more consistent. Jonathon On Tue, Aug 22, 2017 at 3:56 AM, Dario Pennisi via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>

Re: [USRP-users] RFNoC user registers and related APIs

in someway but tags are only a GNUradio concept not in RFNOC. A good start is to utilize the timing information in the headers, but ideally you would just edit the existing radio blocks to make them more useful in general. On Tue, Aug 22, 2017 at 15:57 Dario Pennisi via USRP-users <usrp<mailt

[USRP-users] rfnoc blocks with multiple inputs/outputs

Hi, I am still struggling with a block which should have 2 inputs and 1 output. Apparently everything is fine with both FPGA and software but the second input is not fed with data. I could not find any example of an asymmetric block with different number of inputs/outputs so I am starting to

Re: [USRP-users] rfnoc blocks with multiple inputs/outputs

instantiated and connected to the crossbar in x300_core.v<https://github.com/EttusResearch/fpga/blob/maint/usrp3/top/x300/x300_core.v>. Regards, Michael On Wed, Oct 4, 2017 at 11:57 PM, Dario Pennisi via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> w

Re: [USRP-users] RFNoC Block with 2 inputs and 1 output

You may want to check this:https://www.mail-archive.com/usrp-users@lists.ettus.com/msg03271.html Dario Pennisi On Sat, Oct 14, 2017 at 10:31 AM +0200, "Andrew Thommesen" > wrote: Hi Dario, Thanks. I did try that, but I am

Re: [USRP-users] RFNoC Block with 2 inputs and 1 output

Hi Andy, As I wrote you have to check available bandwidth. For x310 input data is 32 bits at 160 MHz whereas radios run by default at 200 MHz so you won't be able to fit 800 mbyte/sec in a port able to receive just 640 mbyte/sec. Note that setting sampling frequency in rfnoc radio is useless. To

Re: [USRP-users] rfnoc blocks with multiple inputs/outputs

lock_radio_core blocks are instantiated and connected to the crossbar in x300_core.v<https://github.com/EttusResearch/fpga/blob/maint/usrp3/top/x300/x300_core.v>. Regards, Michael On Wed, Oct 4, 2017 at 11:57 PM, Dario Pennisi via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists

Re: [USRP-users] rfnoc block with two inputs

Hi Nick, Thank you for your feedback. I didn't notice src and data Sid are per input however looking at code I don't think this is the problem. My understanding is that src Sid is used to form cvita packet going out of the block. In simple mode axis wrapper doesn't seem to use while it is used

Re: [USRP-users] rfnoc block with two inputs

Hi Nick, Sure. The block is a demodulator so basically it inputs samples and outputs packet bytes in bursts so of course we have rate change. The relevant code is below: cvita_hdr_decoder cvita_hdr_decoder0 ( .header(m_axis0_data_tuser), .pkt_type(), .eob(),.has_time(), .seqnum(),

Re: [USRP-users] rfnoc block with two inputs

Hi, I managed to get a good simulation for the two inputs. I did it by modifying default test bench this way: * localparam NUM_STREAMS= 2; // Number of test bench streams * modified RFNOC_CONNECT to two RFNOC_CONNECT_BLOCK_PORT calls each with a different port. Port 0 of TB

[USRP-users] rfnoc block with two inputs

Hi, We are developing a block which needs two inputs from the two radios. The block works with one input but when adding the second one only the first input is fed with data. Block has noc_shell instantiated with INPUT_PORTS(2) and its str_data output bus is connected to two axi_wrappers.

Re: [USRP-users] rfnoc block with two inputs

Hi, It’s quite complex and long… posting the initial part with shell and wrappers module noc_block_demod #( parameter NOC_ID = 64'h1408E12980FDE75E, parameter MAX_PACKET_SIZE = 64) ( input bus_clk, input bus_rst, input ce_clk, input ce_rst, input [63:0] i_tdata, input i_tlast, input

Re: [USRP-users] rfnoc block with two inputs

Hi, I moved forward a bit but didn't really come up to a solution. In my block I doublechecked the signals which are replicated for each input and made sure they are connected at top level. This turned out to be apparently useless because I only have one output so src_sid and dst_sid for the

[USRP-users] RFNoC user registers and related APIs

Hi, I have some doubts on the interfaces available on noc shell and axi wrapper. Based on the deep dive slides noc shell provides 3 bidirectional busses: * Command & response Looking at the noc_shell code this should be indicated as control source. This bus seems to be able to send commands

[USRP-users] systemverilog files in rfnoc block

hi, i am trying to include a couple of systemverilog files in the list of sources for a custom rfnoc block. if i do that i can see in the log that all files with .sv extension are ignored and of course their modules are not found. if i launch compilation in gui mode and then add files back it

Re: [USRP-users] systemverilog files in rfnoc block

i think i found the issue... tcl script file usrp3/tools/scripts/viv_utils.tcl actually contains instructions to add files to project based on their extensions and .sv is not listed so files are skipped. adding a case for .sv works but it also includes axi_crossbar_intf.sv which seems to be a

[USRP-users] rfnoc burst stream tagging

Hi, i've been developing a packet decoder block in rfnoc and so far it seems to work in the sense that i can successfully decode packets and receive them in gnuradio. in my implementation output data from the block would be in short bursts and i would like to be able on the host to identify

[USRP-users] proposed patch for rfnoc_block_impl.cc

Hi, After some testing it turned out that when creating a rfnoc block that sends timestamps for packets, the output stream is not tagged. The patch below solves the issue and also removes the annoying timeout message that comes out whenever a block is not sending data so often. Hope this helps

Re: [USRP-users] No output from OOT RFNOC Module

Hi, If your block is sending small amounts of bursty data the timeout being printed is irrelevant as it just indicates no data has been sent for a given time lapse not that no data has been received at all. Dario Pennisi On Wed, Oct 11, 2017 at 10:10 PM +0200, "John Medrano via

Re: [USRP-users] rfnoc block with two inputs

Hi nick, Thank you.. the example you posted seems a 1 input 2 output block which is the opposite I'm trying to do. Btw, is there any reason why you seem to be excluding software is an issue? Note that in my case I have a cpp controller as I need to do some custom register programming. I noticed

[USRP-users] issue with RFNoC signal generator block on X310 (TLDR)

Hi, A short question for which there is a larger underlying issue: if I connect a RX RFNoC Radio block to a TX RFNoC radio block, regardless of the presence of FIFOs in the middle nothing gets transmitted. The only way it works seems to be by passing through the host by inserting two fifos and

[USRP-users] EOB marker in RFNoC

Hi, we are working on a packet processor in RFNoC on x310 and we would need to receive EOB markers on the stream port. We developed a block that generates bursts of data on the host side with proper start/end of burst tagging and we fed its output to a custom rfnoc block but we never see EOB

Re: [USRP-users] systemverilog files in rfnoc block

Hi, I pushed the fix on my fork:

Re: [USRP-users] RFNoC Software Emulation

Hi Brian, Don't think what you want to do is feasible. While the streaming data part is easy as it's basically just an oot block, emulating register writes is not possible because they go through APIs that send commands over the network. The only reasonable option I see to do what you want is

Re: [USRP-users] RFNoC Software Emulation

Hi Brian, It really depends on what you want to achieve. If you just want to perform validation then you can use simulation which is already set up and straightforward if you follow the examples. Also it would allow you to verify even hls code and make sure it does what you expect in a cycle

Re: [USRP-users] RFNoC Software Emulation

Hi Brian, I think I understand where you're going but I still think you may have more trouble than solutions. One for all is bandwidth. 10g Ethernet is just able to support one channel at 200 msps. Unless you're downsampling somewhere you won't be able to pass all that bandwidth across the

Re: [USRP-users] RFNoC Software Emulation

Hi Brian, as you may have guessed I’m not from ettus so maybe you can get better insight from them. On my side I would recommend you look at the APIs to write/read registers and the ones that set up streams to/from the device. These are the main building blocks and you will find that the

Re: [USRP-users] how to write test for block with two output ports

Hi ishai, Although a block with different number of inputs and outputs is feasible in rfnoc, uhd won't work well with it so I would suggest you define it with the same number of inputs and outputs and then just connect the unused into to a null source/sink For a complete example on how to

Re: [USRP-users] Error with multiple block output ports

Hi guys, Although rfnoc supports different number of inputs and outputs uhd does not and you'll get all sorts of issues trying to address this. This is the reason why adder block also has a subtract output... Another issue is that loopback within fpga does not work. This means that signals in a

Re: [USRP-users] x300 unrecoverable timeouts

Hi, We recently investigated a similar issue and have a clear understanding on what this comes from. Commands sent by PC to usrp device are responded with an acknowledge. Each command has a sequence number and is sent asynchronously. On the receiving side there is a check on acknowledge

[USRP-users] help with vivado 2017 port

Hi, we're porting our block to the latest Vivado 2017.4 environment but have a few issues we can't explain. 1. Although uhd_usrp_probe finds the blocks with the correct names, it doesn't find the custom control block. This is reported by probe with a warning. Strange thing is that even if

[USRP-users] simulation error with uhd 4.0

Hi, i'm trying to simulate a block where i'm using cmul. in order to have that compiled in i am including the following in my Makefile under rfnoc/fpga in my OOT directory: include $(BASE_DIR)/../lib/ip/Makefile.inc SIM_SRCS = $(abspath rfnoc_block_demod_tb.sv) \

Re: [USRP-users] simulation error with uhd 4.0

> tool instead as it is far more robust than xsim. You can use the vsim make > target to use ModelSim. > > Jonathon > > On Sat, Nov 21, 2020 at 5:54 AM Dario Pennisi via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi, >> i'm trying to simulate a

[USRP-users] ILA in UHD 4

Hi, i am trying to debug my block and to do so i ran GUI=1 make n310_rfnoc_image_core this brings up vivado and allows me to synthesize the design and setup ILA. when i try fitting and generating bitstream i get the following error: [DRC PDRC-29] MMCM_adv_ClkFrequency_clkin1: The calculated

[USRP-users] DPDK with UHD 4.0

Hi, i'm trying to use DPDK with UHD 4 but it is not detected by cmake. i have ubuntu 20.04.1 which installs DPDK 19.11.3-0ubuntu0.2 when i use apt-get install dpdk dpdk-dev i tried passing manually environment variables for include and library directories but that doesn't work. can you please

[USRP-users] rfnoc on uhd4 3.8/9

Hi, I've been trying to create and use a rfnoc block for n310 within gnuradio 3.8 and uhd4.0. I first tried with pybombs but this doesn't not seem to work very well and there is no default recipe that works. I then moved to manual install from source and got something up using the maint-3.8 and

Re: [USRP-users] simulation error with uhd 4.0

you have access to ModelSim, I would highly suggest trying that > tool instead as it is far more robust than xsim. You can use the vsim make > target to use ModelSim. > > Jonathon > > On Sat, Nov 21, 2020 at 5:54 AM Dario Pennisi via USRP-users < > usrp-users@lists.ettus.com