[USRP-users] E310 GPIO ATR not working

[Ethan C]

I'm trying to use the GPIO ATR functionality on an E310 using a 'Python
Snippet' block in Gnuradio. I have code that works this way for a B210 and
am adapting it to work for the E310. However, I have not had any success.
The get_gpio_attr READBACK attribute (reads back input GPIOs but can also
read which output pins are high) print statements indicate GPIO data pin 6
should be high but there is nothing there when checked with a voltmeter.
I'm happy to provide any additional information.
Thanks,
Ethan

E310 GPIO ATR code



#   CHANGING GPIO STATE FOR E310   #



import uhd

ATR_GPIO_MASK = 0b11

# 1=atr 0=manual

ATR_CTRL = 0b11

# 1=output 0=input

ATR_DDR = 0b11

# 1=high on 0=nothing

ATR_0X = 0b10

ATR_RX = 0b01

ATR_TX = 0b001000

ATR_XX = 0b000100

# find usrp device

USRP_E310 = uhd.usrp.MultiUSRP('serial=F644E0')

# find usrp gpio port name

BANK_NAME = USRP_E310.get_gpio_banks(0)[0]

print('\n\n')

print( USRP_E310.get_gpio_attr(BANK_NAME, 'CTRL') )

print( USRP_E310.get_gpio_attr(BANK_NAME, 'DDR') )

print( USRP_E310.get_gpio_attr(BANK_NAME, 'OUT') )

print( USRP_E310.get_gpio_attr(BANK_NAME, 'ATR_0X') )

print( USRP_E310.get_gpio_attr(BANK_NAME, 'ATR_RX') )

print( USRP_E310.get_gpio_attr(BANK_NAME, 'ATR_TX') )

print( USRP_E310.get_gpio_attr(BANK_NAME, 'ATR_XX') )

print( USRP_E310.get_gpio_attr(BANK_NAME, 'READBACK') )

print('\n\n')

# configure gpio for atr operation

USRP_E310.set_gpio_attr(BANK_NAME, 'CTRL', ATR_CTRL, ATR_GPIO_MASK)

USRP_E310.set_gpio_attr(BANK_NAME, 'DDR', ATR_DDR, ATR_GPIO_MASK)

USRP_E310.set_gpio_attr(BANK_NAME, 'ATR_0X', ATR_0X, ATR_GPIO_MASK)

USRP_E310.set_gpio_attr(BANK_NAME, 'ATR_RX', ATR_RX, ATR_GPIO_MASK)

USRP_E310.set_gpio_attr(BANK_NAME, 'ATR_TX', ATR_TX, ATR_GPIO_MASK)

USRP_E310.set_gpio_attr(BANK_NAME, 'ATR_XX', ATR_XX, ATR_GPIO_MASK)

print('\n\n')

print( USRP_E310.get_gpio_attr(BANK_NAME, 'CTRL') )

print( USRP_E310.get_gpio_attr(BANK_NAME, 'DDR') )

print( USRP_E310.get_gpio_attr(BANK_NAME, 'OUT') )

print( USRP_E310.get_gpio_attr(BANK_NAME, 'ATR_0X') )

print( USRP_E310.get_gpio_attr(BANK_NAME, 'ATR_RX') )

print( USRP_E310.get_gpio_attr(BANK_NAME, 'ATR_TX') )

print( USRP_E310.get_gpio_attr(BANK_NAME, 'ATR_XX') )

print( USRP_E310.get_gpio_attr(BANK_NAME, 'READBACK') )

print('\n\n')


Print statement outputs

0

4294967295

0

0

0

0

0

0

63 < CTRL

4294967295 < DDR

0 < OUT

32 < 0X (idle) set for pin 6

16 < RX set for pin 5

8 < TX set for pin 4

4 < XX (full duplex) set for pin 3

32 < READBACK detects high on pin 6
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[USRP-users] Re: E310 cable for GPIO connector

[Ethan C]

That's some great info. Thanks Ray!

On Sun, Feb 25, 2024 at 1:35 PM Ray Roberge  wrote:

> Ethan,
>
> I could never find any pre-wired cable assemblies for the E310 connector,
> but the housing and female pins are cheaply available:
>
> DF20A-10DS-1C HousingDigikey P/N: H3143-ND  $0.30
> each
>
> DF20F-2830SCFA Female Pin... Digikey P/N: H3148CT-ND   $0.10
> each
>
> The crimping tool that is commercially used is very expensive:
> https://www.mouser.com/ProductDetail/Hirose-Connector/HT302-DF20B-2830S?qs=7H2Jq%252ByxpJL7ruPcF4WDUg%3D%3D
> . You might try an alternative crimper, they work.
>
> Good Luck,
> Ray
>
>
>
>
> On Saturday, February 24, 2024 at 09:12:48 PM EST, Ethan C <
> ethanclarke...@gmail.com> wrote:
>
>
> Hello all,
> I am looking for the part number for the GPIO connector (J12) on an E310.
> So that I may buy a cable to connect to it. I can't find any information
> online nor on the physical connector itself on the E310 I have.
>
> Thanks,
> Ethan VA7MNK
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[USRP-users] E310 cable for GPIO connector

[Ethan C]

Hello all,
I am looking for the part number for the GPIO connector (J12) on an E310.
So that I may buy a cable to connect to it. I can't find any information
online nor on the physical connector itself on the E310 I have.

Thanks,
Ethan VA7MNK
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[USRP-users] Re: Implementing B210 GPIO ATR for both channels

[Ethan C]

Progress update time! I figured out a janky way to get the ATR working for
both channel A and channel B. I did it by flipping all of the frontend
mapping bits in b200_impl.cpp

.

[image: image.png]

I checked this fix with a python script to transmit a signal
https://pysdr.org/content/usrp.html, a spectrum analyzer to confirm which
channel was outputting a signal, and a multimeter to confirm the ATR was
working.
With the default setup, the USRP output from channel A with the ATR
working. After flipping all the bits, the USRP output from channel B (while
the python script was still set up to transmit from channel A) with the ATR
still working.

My concern with this fix is I don't know if there are any adverse effects
on the USRP from flipping the frontend ports this way? Such as worse
performance, or harming the frontend circuitry?
Any advice helps, thanks.
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[USRP-users] Re: USRP B210 fpga build error

[Ethan C]

Yep that did the trick, thanks! Kind of embarrassingly simple but at least
I know for next time.

On Wed, Nov 29, 2023 at 12:55 AM Marcus D. Leech 
wrote:

> On 29/11/2023 03:41, Ethan C wrote:
>
> Hello,
> I am trying to build the default B210 fpga project using Xilinx ISE just
> to confirm I can do it before investing more time in a project. I
> downloaded UHD 4.6 from the github repo and in ~uhd/fpga/usrp3/top/b200 set
> up the Xilinx environment and built the fpga project
>
> source /opt/Xilinx/14.7/ISE_DS/settings64.sh
>
> make b210
>
> I get an error "python: No such file or directory" during the "Generating
> Report" part of the build like in the attached screenshots.
>
>
> I don't quite understand the python line before the error, but I assume
> it's calling check_timing.py with b200.twr as a parameter. check_timing.py
> is in the expected location, not sure where build-B200//b200.twr is
> supposed to be, but there is the touch command right before so it should be
> in ~uhd/fpga/usrp3/top/b200.
> The USRP B210 I am using wasn't connected when building the fpga project,
> I assume that loading the new fpga project into the USRP can be done after
> building it
> I edited one file in ~uhd/fpga/usrp3/top/b200 by adding a comment so I
> guess it's not truly default.
> Is there something I'm missing or doing wrong?
>
>
> I looks like there's no program called "python" on your system.
>
> Some distros require that the user decide which of the python2 or python3
> executables should be sym-linked to "python".
>
> You probably haven't done that on your system.
>
>
>
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[USRP-users] USRP B210 fpga build error

[Ethan C]

 Hello,
I am trying to build the default B210 fpga project using Xilinx ISE just to
confirm I can do it before investing more time in a project. I downloaded
UHD 4.6 from the github repo and in ~uhd/fpga/usrp3/top/b200 set up the
Xilinx environment and built the fpga project

source /opt/Xilinx/14.7/ISE_DS/settings64.sh

make b210

I get an error "python: No such file or directory" during the "Generating
Report" part of the build like in the attached screenshots.



I don't quite understand the python line before the error, but I assume
it's calling check_timing.py with b200.twr as a parameter. check_timing.py
is in the expected location, not sure where build-B200//b200.twr is
supposed to be, but there is the touch command right before so it should be
in ~uhd/fpga/usrp3/top/b200.
The USRP B210 I am using wasn't connected when building the fpga project, I
assume that loading the new fpga project into the USRP can be done after
building it
I edited one file in ~uhd/fpga/usrp3/top/b200 by adding a comment so I
guess it's not truly default.
Is there something I'm missing or doing wrong?
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[USRP-users] Implementing B210 GPIO ATR for both channels

[Ethan C]

 

I am planning to use the GPIO ATR on a B210 as a PTT signal. Both channels
will be used on the B210. Currently, GPIO ATR can't be switched from
channel A to channel B on the B210 due to the function not being
implemented in UHD, from EttusResearch/uhd/host/lib/usrp/multi_usrp.cpp


void set_gpio_src(
const std::string&, const std::vector&, const size_t) override
{
throw uhd::not_implemented_error(
"set_gpio_src() not implemented for this motherboard!");
}

Could this functionality be implemented with a script that directly
accesses the ATR or tx/rx status registers? Or would I need to build custom
firmware and modify the UHD drivers? Are there any good resources or
tutorials for how to do either of these things?
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