Re: [USRP-users] Pybombs error for gnuradio
Deleting binary files from previous manual installations worked for me. On Fri, Oct 26, 2018 at 12:19 PM Sumit Kumar wrote: > Hello Pratik, > > Were you able to find the solution ? > > BR > Sumit > > On Wed, Oct 17, 2018 at 9:41 PM Pratik Chatterjee via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hello all, >> >> I have used pybombs in the past and it worked just fine. But recently I >> get compatibility issues of uhd and fpga, as well as the following error >> while building gnuradio. Has anyone seen this before? I am following the >> getting started rfnoc guide. >> >> [ 87%] Building CXX object >> gr-uhd/swig/CMakeFiles/_uhd_swig.dir/uhd_swigPYTHON_wrap.cxx.o >> /home/pratik/rfnoc/src/gnuradio/build/gr-uhd/swig/uhd_swigPYTHON_wrap.cxx: >> In function ‘PyObject* _wrap_time_spec_t___addSWIG_0(PyObject*, >> PyObject*)’: >> /home/pratik/rfnoc/src/gnuradio/build/gr-uhd/swig/uhd_swigPYTHON_wrap.cxx:20964:33: >> error: ‘class uhd::time_spec_t’ has no member named ‘operator+’ >>result = (arg1)->operator +(*arg2); >> ^ >> /home/pratik/rfnoc/src/gnuradio/build/gr-uhd/swig/uhd_swigPYTHON_wrap.cxx: >> In function ‘PyObject* _wrap_time_spec_t___addSWIG_1(PyObject*, >> PyObject*)’: >> /home/pratik/rfnoc/src/gnuradio/build/gr-uhd/swig/uhd_swigPYTHON_wrap.cxx:21009:33: >> error: ‘class uhd::time_spec_t’ has no member named ‘operator+’ >>result = (arg1)->operator +((uhd::time_spec_t const &)*arg2); >> ^ >> gr-uhd/swig/CMakeFiles/_uhd_swig.dir/build.make:70: recipe for target >> 'gr-uhd/swig/CMakeFiles/_uhd_swig.dir/uhd_swigPYTHON_wrap.cxx.o' failed >> make[2]: *** >> [gr-uhd/swig/CMakeFiles/_uhd_swig.dir/uhd_swigPYTHON_wrap.cxx.o] Error 1 >> CMakeFiles/Makefile2:15091: recipe for target >> 'gr-uhd/swig/CMakeFiles/_uhd_swig.dir/all' failed >> make[1]: *** [gr-uhd/swig/CMakeFiles/_uhd_swig.dir/all] Error 2 >> Makefile:160: recipe for target 'all' failed >> make: *** [all] Error 2 >> [ERROR] Build failed. See output above for error messages. >> [ERROR] Problem occurred while building package gnuradio: >> Build failed. >> [ERROR] Error installing package gnuradio. Aborting. >> >> Thanks, >> Pratik >> ___ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> > > > -- > -- > Sumit kumar > Doctoral Student, UPMC > Eurecom, BIOT > France > > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Pybombs error for gnuradio
Hello all, I have used pybombs in the past and it worked just fine. But recently I get compatibility issues of uhd and fpga, as well as the following error while building gnuradio. Has anyone seen this before? I am following the getting started rfnoc guide. [ 87%] Building CXX object gr-uhd/swig/CMakeFiles/_uhd_swig.dir/uhd_swigPYTHON_wrap.cxx.o /home/pratik/rfnoc/src/gnuradio/build/gr-uhd/swig/uhd_swigPYTHON_wrap.cxx: In function ‘PyObject* _wrap_time_spec_t___addSWIG_0(PyObject*, PyObject*)’: /home/pratik/rfnoc/src/gnuradio/build/gr-uhd/swig/uhd_swigPYTHON_wrap.cxx:20964:33: error: ‘class uhd::time_spec_t’ has no member named ‘operator+’ result = (arg1)->operator +(*arg2); ^ /home/pratik/rfnoc/src/gnuradio/build/gr-uhd/swig/uhd_swigPYTHON_wrap.cxx: In function ‘PyObject* _wrap_time_spec_t___addSWIG_1(PyObject*, PyObject*)’: /home/pratik/rfnoc/src/gnuradio/build/gr-uhd/swig/uhd_swigPYTHON_wrap.cxx:21009:33: error: ‘class uhd::time_spec_t’ has no member named ‘operator+’ result = (arg1)->operator +((uhd::time_spec_t const &)*arg2); ^ gr-uhd/swig/CMakeFiles/_uhd_swig.dir/build.make:70: recipe for target 'gr-uhd/swig/CMakeFiles/_uhd_swig.dir/uhd_swigPYTHON_wrap.cxx.o' failed make[2]: *** [gr-uhd/swig/CMakeFiles/_uhd_swig.dir/uhd_swigPYTHON_wrap.cxx.o] Error 1 CMakeFiles/Makefile2:15091: recipe for target 'gr-uhd/swig/CMakeFiles/_uhd_swig.dir/all' failed make[1]: *** [gr-uhd/swig/CMakeFiles/_uhd_swig.dir/all] Error 2 Makefile:160: recipe for target 'all' failed make: *** [all] Error 2 [ERROR] Build failed. See output above for error messages. [ERROR] Problem occurred while building package gnuradio: Build failed. [ERROR] Error installing package gnuradio. Aborting. Thanks, Pratik ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] RFNOC: Gain block testbench not working
Hello, I am running the gain block testbench from the getting started page. The first four tests succeed, however the fifth one keeps running without any conclusive result. Attached is the test result. The other thing I have noticed is that the test result for the first four is less verbose than the one given on the getting started page. Some display statements are missing. Is there a way to make the output more verbose? I am using UHD 4.0.0.rfnoc-devel-409-gec9138eb and Vivado 2015. Thank you, Pratik delta3@delta3-desktop:~/rfnoc/src/rfnoc-tutorial/build$ make noc_block_gain_tb Setting up a 64-bit FPGA build environment for the USRP-E3x0... - Vivado: Found (/opt/Xilinx/Vivado/2015.4/bin) - Vivado HLS: Found (/opt/Xilinx/Vivado_HLS/2015.4/bin) Environment successfully initialized. BUILDER: Checking tools... * GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu) * Python 2.7.12 * Vivado v2015.4 (64-bit) [00:00:00] Executing command: vivado -mode batch -source /home/delta3/rfnoc/src/uhd-fpga/usrp3/tools/scripts/viv_sim_project.tcl -log xsim.log -nojournal [00:00:21] Current task: Synthesis +++ Current Phase: Synthesis [00:00:21] Current task: Synthesis +++ Current Phase: TESTBENCH STARTED: noc_block_gain [00:00:21] [TEST CASE 1] (t=0) BEGIN: Wait for Reset... [00:00:21] Current task: [TEST CASE 1] (t=0) BEGIN: Wait for Reset... +++ Current Phase: TESTBENCH STARTED: noc_block_gain [00:00:21] [TEST CASE 1] (t=01002) DONE... Passed [00:00:21] Current task: [TEST CASE 1] (t=01002) DONE... Passed +++ Current Phase: TESTBENCH STARTED: noc_block_gain [00:00:21] [TEST CASE 2] (t=01002) BEGIN: Check NoC ID... [00:00:21] Current task: [TEST CASE 2] (t=01002) BEGIN: Check NoC ID... +++ Current Phase: TESTBENCH STARTED: noc_block_gain [00:00:21] [TEST CASE 2] (t=01238) DONE... Passed [00:00:21] Current task: [TEST CASE 2] (t=01238) DONE... Passed +++ Current Phase: TESTBENCH STARTED: noc_block_gain [00:00:21] [TEST CASE 3] (t=01238) BEGIN: Connect RFNoC blocks... [00:00:21] Current task: [TEST CASE 3] (t=01238) BEGIN: Connect RFNoC blo[00:00:21] Current task: [TEST CASE 3] (t=01238) BEGIN: Connect RFNoC blo[00:00:22] Current task: [TEST CASE 3] (t=01238) BEGIN: Connect RFNoC blo[00:00:22] Current task: [TEST CASE 3] (t=01238) BEGIN: Connect RFNoC blocks... +++ Current Phase: TESTBENCH STARTED: noc_block_gain [00:00:22] [TEST CASE 3] (t=05457) DONE... Passed [00:00:22] Current task: [TEST CASE 3] (t=05457) DONE... Passed +++ Current Phase: TESTBENCH STARTED: noc_block_gain [00:00:22] [TEST CASE 4] (t=05457) BEGIN: Write / readback user registers... [00:00:22] Current task: [TEST CASE 4] (t=05457) BEGIN: Write / readback [00:00:23] Current task: [TEST CASE 4] (t=05457) BEGIN: Write / readback user registers... +++ Current Phase: TESTBENCH STARTED: noc_block_gain [00:00:23] [TEST CASE 4] (t=06888) DONE... Passed [00:00:23] Current task: [TEST CASE 4] (t=06888) DONE... Passed +++ Current Phase: TESTBENCH STARTED: noc_block_gain [00:00:23] [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:23] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:23] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:24] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:24] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:25] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:25] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:26] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:26] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:27] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:27] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:28] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:28] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:29] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:29] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:30] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:30] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:31] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:31] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:32] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:32] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:33] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:33] Current task: [TEST CASE 5] (t=06888) BEGIN: Test sequence... [00:00:34] Current task: [TEST CASE 5] (t=06888)
[USRP-users] RFNOC: AXI Wrapper Configuration busses
Hi, Can anyone please provide some insight on the use of configuration buses in the axi wrapper - why and when would we want to use them? Do they complement the axis stream signals (m_axis and s_axis) in any way? Thank you, Pratik ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Lookup error: Path not found in tree
I am building a repeater from the UHD and I have Nick's post as reference. My intended flow graph will be: *radio_rx->gain_block(to remove timestamps)->radio_tx* But I keep getting a lookup error (attached). I have isolated the line of error (line 196) however I have not been able to correct it. Is there anything wrong fundamentally in my approach and what does the error mean: *Error: LookupError: Path not found in tree: /mboards/0/dboards/B/tx_frontends/freq/value* Output log: https://paste.ubuntu.com/p/gSnFQCDn9q/ Code: https://paste.ubuntu.com/p/XcFq3PNhZw/ usrp-probe: https://paste.ubuntu.com/p/ps6cRbRH3j/ usrp-probe-tree: https://paste.ubuntu.com/p/VMCWHkn3hW/ ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] Repeater with RFNoc (Can't have TX & RX on same flow diagram)
Thanks Nick for the fast response. Will try this. On Fri, Feb 2, 2018 at 3:35 PM, Nick Foster <bistrom...@gmail.com> wrote: > https://corvid.io/2017/04/22/stupid-rfnoc-tricks-loopback/ should help. > RFNoC does not support loopback "out of the box". > > Nick > > On Fri, Feb 2, 2018 at 12:18 PM Pratik Chatterjee via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi, >> >> This question was posted two years ago (reference link below). I am >> hoping that the problem has been fixed and that I am missing something >> important. Trying to build a simple repeater on X310 using the inbuilt >> blocks: rfnoc radio receive -> rfnoc fifo - > rfnoc radio transmit. Runs >> fine but don't see anything coming out. In fact I don't see the receive LED >> on the front panel as well. >> >> http://lists.ettus.com/pipermail/usrp-users_lists. >> ettus.com/2016-March/019225.html >> >> Thanks, >> Pratik >> ___ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Repeater with RFNoc (Can't have TX & RX on same flow diagram)
Hi, This question was posted two years ago (reference link below). I am hoping that the problem has been fixed and that I am missing something important. Trying to build a simple repeater on X310 using the inbuilt blocks: rfnoc radio receive -> rfnoc fifo - > rfnoc radio transmit. Runs fine but don't see anything coming out. In fact I don't see the receive LED on the front panel as well. http://lists.ettus.com/pipermail/usrp-users_lists. ettus.com/2016-March/019225.html Thanks, Pratik ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] Controlling the temperature controlled oscillator/clock gen
Hi, I have a X310. I am wondering if there is a way to control/access the 10 MHz temperature controlled oscillator/clock gen block using Labview. Thank you in advance. Pratik ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
