[USRP-users] USRP B210 fpga build error
Hello, I am trying to build the default B210 fpga project using Xilinx ISE just to confirm I can do it before investing more time in a project. I downloaded UHD 4.6 from the github repo and in ~uhd/fpga/usrp3/top/b200 set up the Xilinx environment and built the fpga project source /opt/Xilinx/14.7/ISE_DS/settings64.sh make b210 I get an error "python: No such file or directory" during the "Generating Report" part of the build like in the attached screenshots. I don't quite understand the python line before the error, but I assume it's calling check_timing.py with b200.twr as a parameter. check_timing.py is in the expected location, not sure where build-B200//b200.twr is supposed to be, but there is the touch command right before so it should be in ~uhd/fpga/usrp3/top/b200. The USRP B210 I am using wasn't connected when building the fpga project, I assume that loading the new fpga project into the USRP can be done after building it I edited one file in ~uhd/fpga/usrp3/top/b200 by adding a comment so I guess it's not truly default. Is there something I'm missing or doing wrong? ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com
Re: [USRP-users] USRP B210 FPGA Build
On 04/09/2018 02:24 AM, Yeo Jin Kuang Alvin (IA) via USRP-users wrote: > Hi everyone, > > > > I tried to build the USRP B210 FPGA for Xilinx ISE 14.7 (Windows) and I > got this in my cmd prompt: > > > > C:\Users\WORK\Desktop\fpga-maint\usrp3\top\b200>make B210 PROJECT_ONLY=1 > > "ISE Version: Release 14.7 - xtclsh P.20131013 (nt64)" > > make -f Makefile.b200.inc proj NAME=B210 DEVICE=XC6SLX150 > EXTRA_DEFS="TARGET_B21 > > 0=1 " > > make[1]: Entering directory > `C:/Users/WORK/Desktop/fpga-maint/usrp3/top/b200' > > make[1]: *** No rule to make target > `C:/Users/WORK/Desktop/fpga-maint/usrp3/top/ > > b200/C:/Users/WORK/Desktop/fpga-maint/usrp3/lib/fifo/axi_demux4.v', > needed by `b > > uild-B210//b200.xise'. Stop. > > make[1]: Leaving directory `C:/Users/WORK/Desktop/fpga-maint/usrp3/top/b200' > > make: *** [B210] Error 2 > > > > May I know what’s missing? The file axi_demux4.v is located there. This looks like you didn't use the Makefiles. -- M ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
[USRP-users] USRP B210 FPGA Build
Hi everyone, I tried to build the USRP B210 FPGA for Xilinx ISE 14.7 (Windows) and I got this in my cmd prompt: C:\Users\WORK\Desktop\fpga-maint\usrp3\top\b200>make B210 PROJECT_ONLY=1 "ISE Version: Release 14.7 - xtclsh P.20131013 (nt64)" make -f Makefile.b200.inc proj NAME=B210 DEVICE=XC6SLX150 EXTRA_DEFS="TARGET_B21 0=1 " make[1]: Entering directory `C:/Users/WORK/Desktop/fpga-maint/usrp3/top/b200' make[1]: *** No rule to make target `C:/Users/WORK/Desktop/fpga-maint/usrp3/top/ b200/C:/Users/WORK/Desktop/fpga-maint/usrp3/lib/fifo/axi_demux4.v', needed by `b uild-B210//b200.xise'. Stop. make[1]: Leaving directory `C:/Users/WORK/Desktop/fpga-maint/usrp3/top/b200' make: *** [B210] Error 2 May I know what's missing? The file axi_demux4.v is located there. ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
