[USRP-users] check_fpga_compat signature register readback failed

2018-11-19 Thread carry chen via USRP-users
Hi,list today , I find a problem when run usrp b205mini: b200::check_fpga_compat signature register readback failed is the board go bad? Thanks! Carry ___ USRP-users mailing list USRP-users@lists.ettus.com

Re: [USRP-users] Questions regarding BasicTX Daughterboard

2018-11-19 Thread Ian Buckley via USRP-users
Hua, Yes to both questions. If you drive a constant DC amplitude into a USRP sink in GR then you can observe the frequency and phase of the FPGA “digital LO” on an oscilloscope easily. -ian > On Nov 16, 2018, at 9:40 PM, Huacheng Zeng via USRP-users > wrote: > > Dear All: > > I have some

Re: [USRP-users] Bug in timed switching of sample rate

2018-11-19 Thread Fabian Schwartau via USRP-users
Anyone? This is a quite annoying bug and I am having trouble working around it as I cannot meet my timing requirements. Am 20.07.2018 um 11:05 schrieb Fabian Schwartau via USRP-users: Hello everyone, I am experencing some issues when switching the sample rate. I have two synchronized USRP

[USRP-users] Increasing X310 command buffer

2018-11-19 Thread Fabian Schwartau via USRP-users
Hello everyone, is there a way to increase the number of timed commands the X310 can buffer at once? In the default firmware are only a few (can remember exactly, but I think like 5) commands in the queue at maximum which is not enough for my application. Or at least it would be much easier

Re: [USRP-users] X310, basicRX - using all channels in real mode with DDC

2018-11-19 Thread Gwenhael Goavec-Merou via USRP-users
Hello, No ideas, advice or anything else to solve my problem? Thank Gwen On Tue, 6 Nov 2018 22:34:27 +0100 Gwenhael Goavec-Merou via USRP-users wrote: > On Tue, 06 Nov 2018 15:42:10 -0500 > "Marcus D. Leech" wrote: > > > On 11/06/2018 12:23 PM, Gwenhael Goavec-Merou wrote: > > > On Tue,

[USRP-users] RFNoC cannot keep up on large DDC deltas

2018-11-19 Thread Jason Matusiak via USRP-users
I have a problem that I think I have a workaround for, but I would like to understand what is going on if I could. I am guessing that it is a DSPish issue with the way that the DDC is implemented, but I can't quite figure it out. My design had been working on an E310 and I was trying to move

Re: [USRP-users] RFNoC FFT block scaling

2018-11-19 Thread Brian Padalino via USRP-users
On Mon, Nov 19, 2018 at 2:47 PM Rob Kossler via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > Can anyone offer advice regarding the RFNoC FFT scaling argument? It is > not clear to me if this argument should always be left alone or if it > should be adjusted as needed by the user for

Re: [USRP-users] Bug in timed switching of sample rate

2018-11-19 Thread Marcus D. Leech via USRP-users
On 11/19/2018 06:35 AM, Fabian Schwartau via USRP-users wrote: Anyone? This is a quite annoying bug and I am having trouble working around it as I cannot meet my timing requirements. I'm only about 50% certain that sample-rate setting is covered by timed commands. I'll talk to R and get back

Re: [USRP-users] RFNoC FFT block scaling

2018-11-19 Thread Rob Kossler via USRP-users
Thanks. Much appreciated. Rob On Mon, Nov 19, 2018 at 2:54 PM Brian Padalino wrote: > On Mon, Nov 19, 2018 at 2:47 PM Rob Kossler via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi, >> Can anyone offer advice regarding the RFNoC FFT scaling argument? It is >> not clear to me if this