Re: [USRP-users] B210 EMI in GPS band

2019-01-20 Thread d.des via USRP-users
s of > > clocks > > involved in your cabling setup, and determine how to might enter > > one of > > the GNSS bands and how you are going to attenuate them. > > > > Mark-Jan > > > > On Sat, Jan 19, 2019 at 06:36:03PM +, d.des via USRP-users

[USRP-users] B210 EMI in GPS band

2019-01-19 Thread d.des via USRP-users
We've experienced some GPS degradation with the B210 running USB3 that was bad enough to kick us off a small test platform. The only way we've found to reduce the EMI to acceptable levels was to use a USB2 cable to force the controller down to the slower speed, and the bandwidth reduction makes

Re: [USRP-users] RFNoC on E310 -- which uhd version has pre-build FPGA modules?

2019-06-11 Thread d.des via USRP-users
update: as far as I can tell uhd_images_downloader no longer tells the user where on Ettus's server it looks for the files and even with an internet connection it doesn't grab the RFNoC images. However, I was able to look inside the uhd_images_downloader.py file itself and piece together the new

[USRP-users] updated E310 RFNoC guidance

2019-06-09 Thread d.des via USRP-users
The instructions at https://kb.ettus.com/Software_Development_on_the_E3xx_USRP_-_Building_RFNoC_UHD_/_GNU_Radio_/_gr-ettus_from_Source are pretty good and with a little tweaking to account for changes in image file naming and storage location conventions. The process produces a partially-useful

[USRP-users] RFNoC on E310 -- which uhd version has pre-build FPGA modules?

2019-06-11 Thread d.des via USRP-users
I'm still trying to re-create the situation which existed back when https://kb.ettus.com/Software_Development_on_the_E3xx_USRP_-_Building_RFNoC_UHD_/_GNU_Radio_/_gr-ettus_from_Source was written but am not having any luck. Following those insructions I can't get access to any pre-build modules

[USRP-users] updated cross-compile toolchain for E310

2019-06-13 Thread d.des via USRP-users
can anyone provide guidance on finding or creating an updated cross- compile toolchain for the E310? The newest one at http://files.ettus.com/e3xx_images/ won't build recent uhd because of an old cmake and probably more. ___ USRP-users mailing list

[USRP-users] E310 v3.15.0.0 pre-release rfnoc fpga images build but modules not recognized

2019-07-04 Thread d.des via USRP-users
I'm using the new sdk and sd image from http://files.ettus.com/binaries/cache/e3xx/meta-ettus-v3.15.0.0-e310_prerelease/ and have build and run the base and rfnoc images from .../src/uhd/fpga- src/usrp3/top/e31x by following the old tutorial on kb.ettus with just a little updating. it mostly

[USRP-users] E310 v3.15.0.0 pre-release

2019-06-28 Thread d.des via USRP-users
I found the new SD image and cross-compiler described in http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2019-May/059897.html and it seems to work well for the UHD that's pre-installed. I was also able to build the v3.15.0.0 pre-release host code from git and run it from a sshfs

Re: [USRP-users] RFNoC on E310

2019-07-14 Thread d.des via USRP-users
I've wasted a lot of time on this over the past month with the same goal and am just now getting up and running using the sd card image at http://files.ettus.com/binaries/cache/e3xx/meta-ettus-v3.15.0.0-e310_prerelease/ and a recent pull from git: commit 6563c53743617215a18542db7d7050a04a0d409d

Re: [USRP-users] E310 v3.15.0.0 pre-release

2019-06-28 Thread d.des via USRP-users
Marcus Leach wrote: > See this thread here: > http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2016-March/046784.html I understand how it's supposed to work, and it's always worked that way before including in the outdated http://files.ettus.com/e3xx_images/e3xx-release-4/ setup.

Re: [USRP-users] E310 v3.15.0.0 pre-release

2019-06-28 Thread d.des via USRP-users
Marcus Leach wrote: >What happens if you specify an fpga image that doesn't actually >exist? >Does it error out? It ignores the bad file, even though the args seem to be making it pretty far into the process. I still can't find where uhd loads the .bit file. I'm using the version on the

Re: [USRP-users] E310 v3.15.0.0 pre-release

2019-06-28 Thread d.des via USRP-users
Marcus Leach wrote: >What happens if you specify an fpga image that doesn't actually >exist? >Does it error out? It ignores the bad file, even though the args seem to be making it pretty far into the process. I still can't find where uhd loads the .bit file. I'm using the version on the

Re: [USRP-users] latest E310 tutorial

2019-08-13 Thread d.des via USRP-users
e > is a few more minor things fixed in them but can you please give them > and try on your system? I will try to replicate the siggen issue you > ran into. > > > Regards, > Nate Temple > > On Sun, Aug 11, 2019 at 1:38 PM d.des via USRP-users < > usrp-users@lists.et

Re: [USRP-users] problem compiling example rfnoc testbench

2019-08-03 Thread d.des via USRP-users
The trick to making rfnocnodtool work with Vivado Webpack is to edit uhd/fpga-src/usrp3/tools/make/viv_sim_preamble.mak #change the following line #PART_ID = xc7k410t/ffg900/-2 PART_ID = xc7z020/clg484/-1 Don't ask how long it took me to figure this out. I haven't had any luck building any

[USRP-users] rfnoc smallest-footprint integrator+decimator for E310

2019-08-18 Thread d.des via USRP-users
I'm trying to get 10 pounds of processing in a 5-pound radio. I have a homemade signal conditioning block that (should) allow for integration and decimation suitable for low-rate reporting. I've been placing my block between the radio and the stock DDC but the DDC does more than I need and takes a

Re: [USRP-users] latest E310 tutorial

2019-08-11 Thread d.des via USRP-users
Thanks, Royce, that fixed the usrp side of both fosphor and my block! I also made two minor tweaks to the host side to get fosphor working on my PC. These are probably things that a Gnuradio expert would see right away but in case there's anyone else out there who primarily uses the c++ uhd

Re: [USRP-users] Addsub HLS Block Error

2019-09-06 Thread d.des via USRP-users
Nick- Could you share the tricks to remove one of the output ports? I don't I'm having similar issues with my modified addsub block and don't have enough room on the e310 fpga for extra fifos. It's not obvious from the noc_block_addsub code, the use of splitstream and dummy variables is very

[USRP-users] E310 RFNoC frequency change breaks channel time alignment

2019-09-06 Thread d.des via USRP-users
I have a two-channel signal conditioning block based on noc_block_addsub between the radio and a DDC. The entire flowgraph is radio(2 channels out)->addsub(2 channels in and out)-> two separate ZMQ Push Sinks. I'm using the DDC as an integrator/decimator because a pair of FIRs or moving average

Re: [USRP-users] Addsub HLS Block Error

2019-09-07 Thread d.des via USRP-users
a super useful thing to have an add/sub block, > instead of an addsub block. A register-controlled mux to select which > operation you want. I'll think about adding that to the Theseus Cores > project. > > Nick > > On Fri, Sep 6, 2019 at 3:18 PM d.des via USRP-users <

Re: [USRP-users] Addsub HLS Block Error

2019-09-06 Thread d.des via USRP-users
t; project. > > Nick > > On Fri, Sep 6, 2019 at 3:18 PM d.des via USRP-users < > usrp-users@lists.ettus.com> wrote: > > Nick- > > Could you share the tricks to remove one of the output ports? I > > don't > > I'm having similar issues with my modified addsub b

[USRP-users] is there an E310 configuration with clean RF on both channels?

2019-07-20 Thread d.des via USRP-users
The good news is that my RFNoC module does what I want it to do. The bad news is that every version of UHD I've tried it on has serious RF quality issues on one or both channels. I don't remember this from the last time I use E310s about 5 years ago so my next step is to find step back SD images

[USRP-users] E310 Channel 0 dead

2019-07-17 Thread d.des via USRP-users
I've been testing RFNoC Blocks on the E310 using the SD image from http://files.ettus.com/binaries/cache/e3xx/meta-ettus-v3.15.0.0-e310_prerelease/ and a recent pull from git: commit 6563c53743617215a18542db7d7050a04a0d409d (HEAD, tag: v3.15.0.0- e310_prerelease). I got my RFNoC images doing

Re: [USRP-users] USRP E312 configuration

2019-07-18 Thread d.des via USRP-users
At the risk of being repetitive, has anyone reading this checked to see if anything but receiver noise is coming out of Radio Port 0? As of a git pull of 3.15 last night Channel 1 looks great but Channel 0 is still useless for me. It's as if neither antenna switch is connected even though the

[USRP-users] the VCRX2_V2 bone's connected to the ... antenna switch?

2019-07-25 Thread d.des via USRP-users
I'm still trying to revive Channel 0 on the E310 in UHD 3.15. I've swapped SD cards with 3.15 from http://files.ettus.com/binaries/cache/e3xx/meta-ettus-v3.15.0.0-e310_prerelease/ and several older UHD versions such as http://files.ettus.com/e3xx_images/e3xx-release-4/ in several E310 radios

Re: [USRP-users] Addsub HLS Block Error -- this time with script and log -- ignore last email

2019-09-21 Thread d.des via USRP-users
I've been a little embarassed at still not getting this so spent quite a bit of time trying to figure it out before replying -- with no luck. At this point you've provided everying except the gnuradio script so maybe that last piece will fix it. Here is my script and my output. I'm putting the add

Re: [USRP-users] E310 v3.15.0.0 pre-release rfnoc fpga images build but modules not recognized

2019-07-06 Thread d.des via USRP-users
It turns out that I was building the same image over and over again. uhd_image_builder.py doesn't work out of the box for the e310 because of the directory name change at top from e300 to e31x. I'd modified a line: build_dir = { : #'e310':'e300', 'e310':'e31x', : This

[USRP-users] RFNoC Radio+DDC vs USRP source

2019-12-06 Thread d.des via USRP-users
If I build an FPGA image that includes a radio and a DDC and use the Gnuradio USRP block to record 2-channel data on pulsed signals at a 1 MHz sample rate it runs fine and the streams are time aligned. If I build a simple flowgraph with the RFNoC radio+DDC it also runs fine but the samples are

[USRP-users] RFNoC time-allign 2-channel TwinRX -- timed commands?

2019-12-05 Thread d.des via USRP-users
I'm trying to process multi-channel RFNoC streams in Gnuradio but would settle for using the c++ API if necessary. I'm using just one of the two TwinRX card in an X310. The simplest example of the alignment issue is seem by comparing 2-channel recordings made at a 1 MHz sample rate on an aperiodic

Re: [USRP-users] RFNoC time-allign 2-channel TwinRX -- timed commands?

2019-12-05 Thread d.des via USRP-users
Nothing beats the doctor's office effect. In case anyone else has been looking for this I just got it: in c++: : stream_cmd.stream_now = false; //true; //change this line stream_cmd.time_spec = radio_ctrl->get_time_now()+1.5; //or prob. less rx_stream->issue_stream_cmd(stream_cmd); //existing