Hi All,
I am trying to measure the phase difference of a received signal between
the two RX ports of the B210. (In the grc I simply ran each of the two
received signals through an FFT, took the bin with highest amplitude and
extracted it's phase, and finaly - subtracted the two).
I experimented
the other by at least
1/6 of a wavelength, whilst the phase diff was only 1/10 of 2*pi.
Am I understood?
Does anyone have a clue what's going wrong?
Thanks again,
Steve
On 05/07/2018 11:11 AM, shachar J. brown via USRP-users wrote:
>* Hi All,
*> >* I am trying to measure the phase d
*>* Still seems far away from 18 degrees, so cant help more than above...
*> >>* On May 8, 2018 at 11:17 AM "shachar J. brown via USRP-users"
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com>>
wrote:
*>> >>* Hi Jeff,
*>>* Thanks for y
?
Steve
On Tue, May 8, 2018 at 9:17 PM, Reinhold Frederick William Hollender <
whollen...@gmail.com> wrote:
>
>
> On Tue, May 8, 2018 at 12:23 PM, shachar J. brown via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Thanks everyone for trying to sort this
s will be initialized with COEFFS_VEC
>> and the filter will always be ready to go. Also, the output will not
>> be corrupted while loading new coefficients.
>>
>> I would suggest enabling USE_EMBEDDED_REGS_COEFFS unless you plan to
>> constantly change coefficient
's an excellent example.
>> Do you know what are the memory size restrictions of the configuration
>> data?
>>
>> On Thu, Jun 7, 2018 at 10:50 AM, Nick Foster
>> wrote:
>>
>>> Look at the RFNoC FIR filter block for a good example of pushing
>>> configur
Hi All,
I've tried the following simple experiment with my brand new X310 (UBX-160
daughterboards):
GRC Signal Source -->> Throttle -->> DMA FIFO
-->> USRP Radio
I assigned ZERO AMPLITUDE to the signal source, USRP had central frequency
of 1.5 [GHz] and gain of 20.
e possible on an X310, which
> is 195.3125 kS/s, will require that the sending end has more than 6.25 Mb/s
> of continuously available uplink. That is actually not that little, so
> unprocessed samples are seldom what you'd want to send over the internet!
>
> Best regards,
> Marcus
Hi Everyone,
As I've noted in the past, I've started examining the various tools to
export data from the grc via the web. Once again, a disclaimer: My
knowledge in communications is sparse.
Up till now I've successfully accessed gr methods from a remote PC using
the XMLRPC block. cheers.
I want
Hi all,
I'm working on an X310.
I have large data (tables of 1-3 K of variables) I would like to insert
into the FPGA's memory registers while running.
How much space is available in the FPGA? Seemingly, the Address for the
"set_register" is only 8 bits long, and the first 128 addresses are
gs bus.
>
> On Thu, Jun 7, 2018, 8:25 AM shachar J. brown via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hi all,
>>
>> I'm working on an X310.
>>
>> I have large data (tables of 1-3 K of variables) I would like to insert
>> into the
Hi Marcus,
Thanks for replying.
To make the story short - I am trying to collaborate with a colleague of
mine. He has some serious signal processing capabilities on his Windows PC
and I would like to extract the data for him from the X310 (with some minor
processing). His tools don't work well
2 PM, Derek Kozel <derek.ko...@ettus.com>
>>> wrote:
>>>
>>>> Hello Steve,
>>>>
>>>> Can you directly use the X310 from the Windows PC? UHD is fully
>>>> supported on Windows 7 to 10.
>>>>
>>>> Regards,
>
Hi all,
Disclaimer: I have never used zmq before.
My goal is to control a X310 from a remote PC, and receive data. using ZMQ.
I downloaded the simple example zmq_stream.grc:
https://github.com/gnuradio/gnuradio/blob/master/gr-zeromq/examples/zmq_stream.grc
I ran the flow-graph on two
Hi Everyone,
I have noticed the previous discussion on the matter from February 2017,
but seemingly there hasn't been any resolution.
I have worked up till now on B210 and X310. I am now trying to set up a
brand new E310.
I carefully followed the instructions given at
Hi Everyone,
I have created a source block with two output ports using the rfnocmodtool.
My first question concerns the implementation of the axi_wrappers: I have
inserted two axi_wrappers, one for each port (Full code below). Is there
any more preferable way to construct the axi_wrapper
Hi everyone,
I'm having trouble creating a new gr block for my e310.
I compiled uhd and gnuradio from source as instructed in the following page:
https://kb.ettus.com/Software_Development_on_the_E310_and_E312
Now, when I try using the "gr_modtool newmod" command on my development
device (pc), I
Hi all,
I'm trying to create a "complex-to-phase" by using the arctan within the
Xilinx CORDIC IP.
(Part of a simple fft-->1-in-N-->to-phase scheme).
Quite frankly I am a bit confused with the different bit representations.
According to the Xilinx manual (
Hi All,
As I understand it, the B210 has maximum master clock rate of 61.44[MHz]
for one channel, and 30.72 [MHz] per-channel while using two channels.
I am receiving through two channels, and would like to use a sample rate of
20[MHz] with central freq. of 98 [MHz]. I set the master frequency
Hi Everyone,
I'm extremely interested in the precise RX chain propagation delay of the
X310. That would include the full time delay of an arriving signal
throughout the rx frontend, ADC, until arrival to the first RFNoC block on
the FPGA.
Surely someone must have deeply studied the matter... Any
Hi Everyone,
I have built a couple of RFNOC blocks (using rfnocmodtool), connected them
using the GRC, and ran the scheme on an X310.
My objective now is to measure the precise latency of each block. In other
words, I would like to run the complete flow and see any indication of the
signal
Hi,
I'm working on an X310. All GRC blocks are working fine, including UHD
source & sink block.
However, when I try to include an RFNOC radio block, I get the following
error:
...
Ooverrun on chan 0
Doverrun on chan D0
overrun on chan 0
overrun on chan 0
DDterminate called after throwing an
Hi all,
I have been working for a long while with rfnoc on an X310.
I have lately upgraded the rfnoc, and now when I try to run
uhd_image_builder.py I receive an error indicating I need Vivado 2018.12,
while my licence is for 2018.3. Upgrading the Vivado is currently not
available.
1. Is there
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