Re: [USRP-users] Build E310_sg3.bit problem

2018-05-20 Thread Nicolas Cuervo via USRP-users 
Hello Artyom,

Unfortunately, this is something we are aware of and has to do with the
high utilization that the DDCs and DUC blocks are taking. We are actively
working on reducing the FPGA utilization of these blocks in order to make
this build possible.

Regards,
- Nicolas


On Sun, May 20, 2018 at 4:27 PM, Artyom Asadchy via USRP-users <
usrp-users@lists.ettus.com> wrote:

> 2017.4
>
> вс, 20 мая 2018 г., 17:25 Marcus Müller :
>
>> Interesting!
>> What's your Vivado version?
>>
>> On 20 May 2018 13:44:28 GMT+02:00, Artyom Asadchy 
>> wrote:
>>>
>>> Hello, Marcus.
>>> Yes. this is the unmodified image. I clone it from
>>> https://github.com/EttusResearch/fpga, checkout to rfnoc-devel (in my
>>> case commit d1d683bcd87bd3cea56f9654152b53e4830db612), than navigate to
>>> "usrp3/top/e300", run "source setupenv.sh" and "make E310_sg3".
>>> Best regards, Artyom.
>>>
>>> 2018-05-20 11:13 GMT+03:00 Marcus Müller :
>>>
 Hello Artjom,

 Is this the unmodified image? The error basically complains about too
 much logic to put on the FPGA, and that doesn't happen with our stock
 images. How are you building this?

 Best regards,
 Marcus


 On 19 May 2018 20:16:40 GMT+02:00, "Артем Асадчий via USRP-users" <
 usrp-users@lists.ettus.com> wrote:
>
> Hi everyone,
>
> I've got a problem, when try to build E310_sg3.bit:
>
> ERROR: [Place 30-487] The packing of instances into the device could
> not be obeyed. There are a total of 13300 slices in the pblock, of which
> 7850 slices are available, however, the unplaced instances require 9752
> slices. Please analyze your design to determine if the number of LUTs, 
> FFs,
> and/or control sets can be reduced.
> ERROR: [Place 30-99] Placer failed with error: 'Detail Placement
> failed please check previous errors for details.'
> [00:10:36] Current task: Placer +++ Current Phase: 3.5 Small Shape
> Detail PlacemERROR: [Common 17-69] Command failed: Placer could not place
> all instances
> [00:10:37] Current task: Placer +++ Current Phase: 3.5 Small Shape
> Detail Placement
> [00:10:37] Current task: Placer +++ Current Phase: Finished
> [00:10:37] Process terminated. Status: Failure
>
> 
> Warnings:   560
> Critical Warnings:  39
> Errors: 3
>
> Makefile.e300.inc:103: recipe for target 'bin' failed
> make[1]: *** [bin] Error 1
> make[1]: Leaving directory '/home/artyom/workspace/ettus/
> rfnoc/uhd/fpga-src/usrp3/top/e300'
> Makefile:63: recipe for target 'E310_sg3' failed
> make: *** [E310_sg3] Error 2
>
> How can i solve this problem?
>
>
 --
 This was written on my cellular phone. whilst an impressive piece of
 engineering, this might not be the perfect device to write emails on -
 please excuse my brevity.

>>>
>>>
>> --
>> This was written on my cellular phone. whilst an impressive piece of
>> engineering, this might not be the perfect device to write emails on -
>> please excuse my brevity.
>>
>
> ___
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Re: [USRP-users] Build E310_sg3.bit problem

2018-05-20 Thread Artyom Asadchy via USRP-users 
2017.4

вс, 20 мая 2018 г., 17:25 Marcus Müller :

> Interesting!
> What's your Vivado version?
>
> On 20 May 2018 13:44:28 GMT+02:00, Artyom Asadchy 
> wrote:
>>
>> Hello, Marcus.
>> Yes. this is the unmodified image. I clone it from https://github.com/
>> EttusResearch/fpga, checkout to rfnoc-devel (in my case commit
>> d1d683bcd87bd3cea56f9654152b53e4830db612), than navigate to
>> "usrp3/top/e300", run "source setupenv.sh" and "make E310_sg3".
>> Best regards, Artyom.
>>
>> 2018-05-20 11:13 GMT+03:00 Marcus Müller :
>>
>>> Hello Artjom,
>>>
>>> Is this the unmodified image? The error basically complains about too
>>> much logic to put on the FPGA, and that doesn't happen with our stock
>>> images. How are you building this?
>>>
>>> Best regards,
>>> Marcus
>>>
>>>
>>> On 19 May 2018 20:16:40 GMT+02:00, "Артем Асадчий via USRP-users" <
>>> usrp-users@lists.ettus.com> wrote:

 Hi everyone,

 I've got a problem, when try to build E310_sg3.bit:

 ERROR: [Place 30-487] The packing of instances into the device could
 not be obeyed. There are a total of 13300 slices in the pblock, of which
 7850 slices are available, however, the unplaced instances require 9752
 slices. Please analyze your design to determine if the number of LUTs, FFs,
 and/or control sets can be reduced.
 ERROR: [Place 30-99] Placer failed with error: 'Detail Placement failed
 please check previous errors for details.'
 [00:10:36] Current task: Placer +++ Current Phase: 3.5 Small Shape
 Detail PlacemERROR: [Common 17-69] Command failed: Placer could not place
 all instances
 [00:10:37] Current task: Placer +++ Current Phase: 3.5 Small Shape
 Detail Placement
 [00:10:37] Current task: Placer +++ Current Phase: Finished
 [00:10:37] Process terminated. Status: Failure

 
 Warnings:   560
 Critical Warnings:  39
 Errors: 3

 Makefile.e300.inc:103: recipe for target 'bin' failed
 make[1]: *** [bin] Error 1
 make[1]: Leaving directory '/home/artyom/workspace/ettus/
 rfnoc/uhd/fpga-src/usrp3/top/e300'
 Makefile:63: recipe for target 'E310_sg3' failed
 make: *** [E310_sg3] Error 2

 How can i solve this problem?


>>> --
>>> This was written on my cellular phone. whilst an impressive piece of
>>> engineering, this might not be the perfect device to write emails on -
>>> please excuse my brevity.
>>>
>>
>>
> --
> This was written on my cellular phone. whilst an impressive piece of
> engineering, this might not be the perfect device to write emails on -
> please excuse my brevity.
>
___
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Re: [USRP-users] Build E310_sg3.bit problem

2018-05-20 Thread Marcus Müller via USRP-users 
Interesting!
What's your Vivado version?

On 20 May 2018 13:44:28 GMT+02:00, Artyom Asadchy  wrote:
>Hello, Marcus.
>Yes. this is the unmodified image. I clone it from
>https://github.com/EttusResearch/fpga, checkout to rfnoc-devel (in my
>case
>commit d1d683bcd87bd3cea56f9654152b53e4830db612), than navigate to
>"usrp3/top/e300", run "source setupenv.sh" and "make E310_sg3".
>Best regards, Artyom.
>
>2018-05-20 11:13 GMT+03:00 Marcus Müller :
>
>> Hello Artjom,
>>
>> Is this the unmodified image? The error basically complains about too
>much
>> logic to put on the FPGA, and that doesn't happen with our stock
>images.
>> How are you building this?
>>
>> Best regards,
>> Marcus
>>
>>
>> On 19 May 2018 20:16:40 GMT+02:00, "Артем Асадчий via USRP-users" <
>> usrp-users@lists.ettus.com> wrote:
>>>
>>> Hi everyone,
>>>
>>> I've got a problem, when try to build E310_sg3.bit:
>>>
>>> ERROR: [Place 30-487] The packing of instances into the device could
>not
>>> be obeyed. There are a total of 13300 slices in the pblock, of which
>7850
>>> slices are available, however, the unplaced instances require 9752
>slices.
>>> Please analyze your design to determine if the number of LUTs, FFs,
>and/or
>>> control sets can be reduced.
>>> ERROR: [Place 30-99] Placer failed with error: 'Detail Placement
>failed
>>> please check previous errors for details.'
>>> [00:10:36] Current task: Placer +++ Current Phase: 3.5 Small Shape
>Detail
>>> PlacemERROR: [Common 17-69] Command failed: Placer could not place
>all
>>> instances
>>> [00:10:37] Current task: Placer +++ Current Phase: 3.5 Small Shape
>Detail
>>> Placement
>>> [00:10:37] Current task: Placer +++ Current Phase: Finished
>>> [00:10:37] Process terminated. Status: Failure
>>>
>>> 
>>> Warnings:   560
>>> Critical Warnings:  39
>>> Errors: 3
>>>
>>> Makefile.e300.inc:103: recipe for target 'bin' failed
>>> make[1]: *** [bin] Error 1
>>> make[1]: Leaving directory '/home/artyom/workspace/ettus/
>>> rfnoc/uhd/fpga-src/usrp3/top/e300'
>>> Makefile:63: recipe for target 'E310_sg3' failed
>>> make: *** [E310_sg3] Error 2
>>>
>>> How can i solve this problem?
>>>
>>>
>> --
>> This was written on my cellular phone. whilst an impressive piece of
>> engineering, this might not be the perfect device to write emails on
>-
>> please excuse my brevity.
>>

-- 
This was written on my cellular phone. whilst an impressive piece of 
engineering, this might not be the perfect device to write emails on - please 
excuse my brevity.___
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Re: [USRP-users] Build E310_sg3.bit problem

2018-05-20 Thread Artyom Asadchy via USRP-users 
Hello, Marcus.
Yes. this is the unmodified image. I clone it from
https://github.com/EttusResearch/fpga, checkout to rfnoc-devel (in my case
commit d1d683bcd87bd3cea56f9654152b53e4830db612), than navigate to
"usrp3/top/e300", run "source setupenv.sh" and "make E310_sg3".
Best regards, Artyom.

2018-05-20 11:13 GMT+03:00 Marcus Müller :

> Hello Artjom,
>
> Is this the unmodified image? The error basically complains about too much
> logic to put on the FPGA, and that doesn't happen with our stock images.
> How are you building this?
>
> Best regards,
> Marcus
>
>
> On 19 May 2018 20:16:40 GMT+02:00, "Артем Асадчий via USRP-users" <
> usrp-users@lists.ettus.com> wrote:
>>
>> Hi everyone,
>>
>> I've got a problem, when try to build E310_sg3.bit:
>>
>> ERROR: [Place 30-487] The packing of instances into the device could not
>> be obeyed. There are a total of 13300 slices in the pblock, of which 7850
>> slices are available, however, the unplaced instances require 9752 slices.
>> Please analyze your design to determine if the number of LUTs, FFs, and/or
>> control sets can be reduced.
>> ERROR: [Place 30-99] Placer failed with error: 'Detail Placement failed
>> please check previous errors for details.'
>> [00:10:36] Current task: Placer +++ Current Phase: 3.5 Small Shape Detail
>> PlacemERROR: [Common 17-69] Command failed: Placer could not place all
>> instances
>> [00:10:37] Current task: Placer +++ Current Phase: 3.5 Small Shape Detail
>> Placement
>> [00:10:37] Current task: Placer +++ Current Phase: Finished
>> [00:10:37] Process terminated. Status: Failure
>>
>> 
>> Warnings:   560
>> Critical Warnings:  39
>> Errors: 3
>>
>> Makefile.e300.inc:103: recipe for target 'bin' failed
>> make[1]: *** [bin] Error 1
>> make[1]: Leaving directory '/home/artyom/workspace/ettus/
>> rfnoc/uhd/fpga-src/usrp3/top/e300'
>> Makefile:63: recipe for target 'E310_sg3' failed
>> make: *** [E310_sg3] Error 2
>>
>> How can i solve this problem?
>>
>>
> --
> This was written on my cellular phone. whilst an impressive piece of
> engineering, this might not be the perfect device to write emails on -
> please excuse my brevity.
>
___
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Re: [USRP-users] Build E310_sg3.bit problem

2018-05-20 Thread Marcus Müller via USRP-users 
Hello Artjom,

Is this the unmodified image? The error basically complains about too much 
logic to put on the FPGA, and that doesn't happen with our stock images. How 
are you building this?

Best regards,
Marcus

On 19 May 2018 20:16:40 GMT+02:00, "Артем Асадчий via USRP-users" 
 wrote:
>Hi everyone,
>
>I've got a problem, when try to build E310_sg3.bit:
>
>ERROR: [Place 30-487] The packing of instances into the device could
>not be
>obeyed. There are a total of 13300 slices in the pblock, of which 7850
>slices are available, however, the unplaced instances require 9752
>slices.
>Please analyze your design to determine if the number of LUTs, FFs,
>and/or
>control sets can be reduced.
>ERROR: [Place 30-99] Placer failed with error: 'Detail Placement failed
>please check previous errors for details.'
>[00:10:36] Current task: Placer +++ Current Phase: 3.5 Small Shape
>Detail
>PlacemERROR: [Common 17-69] Command failed: Placer could not place all
>instances
>[00:10:37] Current task: Placer +++ Current Phase: 3.5 Small Shape
>Detail
>Placement
>[00:10:37] Current task: Placer +++ Current Phase: Finished
>[00:10:37] Process terminated. Status: Failure
>
>
>Warnings:   560
>Critical Warnings:  39
>Errors: 3
>
>Makefile.e300.inc:103: recipe for target 'bin' failed
>make[1]: *** [bin] Error 1
>make[1]: Leaving directory '/home/artyom/workspace/ettus/
>rfnoc/uhd/fpga-src/usrp3/top/e300'
>Makefile:63: recipe for target 'E310_sg3' failed
>make: *** [E310_sg3] Error 2
>
>How can i solve this problem?

-- 
This was written on my cellular phone. whilst an impressive piece of 
engineering, this might not be the perfect device to write emails on - please 
excuse my brevity.___
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[USRP-users] Build E310_sg3.bit problem

2018-05-19 Thread Артем Асадчий via USRP-users 
Hi everyone,

I've got a problem, when try to build E310_sg3.bit:

ERROR: [Place 30-487] The packing of instances into the device could not be
obeyed. There are a total of 13300 slices in the pblock, of which 7850
slices are available, however, the unplaced instances require 9752 slices.
Please analyze your design to determine if the number of LUTs, FFs, and/or
control sets can be reduced.
ERROR: [Place 30-99] Placer failed with error: 'Detail Placement failed
please check previous errors for details.'
[00:10:36] Current task: Placer +++ Current Phase: 3.5 Small Shape Detail
PlacemERROR: [Common 17-69] Command failed: Placer could not place all
instances
[00:10:37] Current task: Placer +++ Current Phase: 3.5 Small Shape Detail
Placement
[00:10:37] Current task: Placer +++ Current Phase: Finished
[00:10:37] Process terminated. Status: Failure


Warnings:   560
Critical Warnings:  39
Errors: 3

Makefile.e300.inc:103: recipe for target 'bin' failed
make[1]: *** [bin] Error 1
make[1]: Leaving directory '/home/artyom/workspace/ettus/
rfnoc/uhd/fpga-src/usrp3/top/e300'
Makefile:63: recipe for target 'E310_sg3' failed
make: *** [E310_sg3] Error 2

How can i solve this problem?
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