Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP
Hi Martin, I was able to run the simulation when I modified setupenv_base.sh to replace the default path to Vivado with my custom path ( I think it should be the same as --vivado-path= ) and also "source uhd-fpga/usrp3/top/x300/setupenv.sh". Thank you. Best, Tien On Tue, Sep 4, 2018 at 5:33 PM Martin Braun via USRP-users < usrp-users@lists.ettus.com> wrote: > On Fri, Feb 09, 2018 at 12:44:26PM -0500, Dang tien Vo-Huu wrote: > >Hi Martin, > >I am on branch rfnoc-devel at version > >b0890fa97ef3dc7d90ed8047d678ca280c72ad61, and I am using Vivado 2015.4 > >- > >tienvh@gl502vm:~/workspace/rfnoc/src/uhd-fpga$ git branch > >* rfnoc-devel > >tienvh@gl502vm:~/workspace/rfnoc/src/uhd-fpga$ git log > >commit b0890fa97ef3dc7d90ed8047d678ca280c72ad61 > >Author: Nicolas Cuervo > >Date:  Tue Sep 19 20:03:43 2017 +0200 > >  image_builder_gui: fix include_dir argument > >- > >I am able to run 'make xsim' now when 'source setupenv.sh' as > suggested in > >the error. > >I think the issue is because I have Vivado installed in other place > than > >/opt/Xilinx/. Although I have modified > >uhd-fpga/usrp3/tools/scripts/setupenv_base.sh for path to VIvado, > 'make > >xsim' doesn't seem to touch it when running. > > Did you try running setup_env.sh --vivado-path=? > > -- M > >Tien > >On Fri, Feb 9, 2018 at 11:05 AM, Martin Braun via USRP-users > > wrote: > > > > On 01/30/2018 08:08 AM, Dang tien Vo-Huu via USRP-users wrote: > > > Hi Jonathon, > > > Thank you for the hint. Actually your suggestion was the first > thing I > > > tried but it didn't work. It threw the error: > > > > > > > > tienvh@gl502vm > :~/workspace/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_fft_tb$ > > > make xsim > > > BUILDER: Checking tools... > > > * GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu) > > > * Python 2.7.12 > > > * ERROR: Vivado not found in environment. Please run setupenv.sh > > > > > > /home/tienvh/workspace/rfnoc/src/uhd-fpga/usrp3/top/../tools/make/viv_preamble.mak:47: > > > recipe for target '.check_tool' failed > > > make: *** [.check_tool] Error 1 > > > > Which branch are you on, and which version of Vivado do you have > > installed? > > -- M > > ___ > > USRP-users mailing list > > USRP-users@lists.ettus.com > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP
On Fri, Feb 09, 2018 at 12:44:26PM -0500, Dang tien Vo-Huu wrote: >Hi Martin, >I am on branch rfnoc-devel at version >b0890fa97ef3dc7d90ed8047d678ca280c72ad61, and I am using Vivado 2015.4 >- >tienvh@gl502vm:~/workspace/rfnoc/src/uhd-fpga$ git branch >* rfnoc-devel >tienvh@gl502vm:~/workspace/rfnoc/src/uhd-fpga$ git log >commit b0890fa97ef3dc7d90ed8047d678ca280c72ad61 >Author: Nicolas Cuervo >Date:  Tue Sep 19 20:03:43 2017 +0200 >  image_builder_gui: fix include_dir argument >- >I am able to run 'make xsim' now when 'source setupenv.sh' as suggested in >the error. >I think the issue is because I have Vivado installed in other place than >/opt/Xilinx/. Although I have modified >uhd-fpga/usrp3/tools/scripts/setupenv_base.sh for path to VIvado, 'make >xsim' doesn't seem to touch it when running. Did you try running setup_env.sh --vivado-path=? -- M >Tien >On Fri, Feb 9, 2018 at 11:05 AM, Martin Braun via USRP-users > wrote: > > On 01/30/2018 08:08 AM, Dang tien Vo-Huu via USRP-users wrote: > > Hi Jonathon, > > Thank you for the hint. Actually your suggestion was the first thing I > > tried but it didn't work. It threw the error: > > > > > > tienvh@gl502vm:~/workspace/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_fft_tb$ > > make xsim > > BUILDER: Checking tools... > > * GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu) > > * Python 2.7.12 > > * ERROR: Vivado not found in environment. Please run setupenv.sh > > > > /home/tienvh/workspace/rfnoc/src/uhd-fpga/usrp3/top/../tools/make/viv_preamble.mak:47: > > recipe for target '.check_tool' failed > > make: *** [.check_tool] Error 1 > > Which branch are you on, and which version of Vivado do you have > installed? > -- M > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com signature.asc Description: PGP signature ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP
Hi Martin, I am on branch rfnoc-devel at version b0890fa97ef3dc7d90ed8047d678ca280c72ad61, and I am using Vivado 2015.4 - tienvh@gl502vm:~/workspace/rfnoc/src/uhd-fpga$ git branch * rfnoc-devel tienvh@gl502vm:~/workspace/rfnoc/src/uhd-fpga$ git log commit b0890fa97ef3dc7d90ed8047d678ca280c72ad61 Author: Nicolas Cuervo Date: Tue Sep 19 20:03:43 2017 +0200 image_builder_gui: fix include_dir argument - I am able to run 'make xsim' now when 'source setupenv.sh' as suggested in the error. I think the issue is because I have Vivado installed in other place than /opt/Xilinx/. Although I have modified uhd-fpga/usrp3/tools/scripts/setupenv_base.sh for path to VIvado, 'make xsim' doesn't seem to touch it when running. Tien On Fri, Feb 9, 2018 at 11:05 AM, Martin Braun via USRP-users < usrp-users@lists.ettus.com> wrote: > On 01/30/2018 08:08 AM, Dang tien Vo-Huu via USRP-users wrote: > > Hi Jonathon, > > Thank you for the hint. Actually your suggestion was the first thing I > > tried but it didn't work. It threw the error: > > > > tienvh@gl502vm:~/workspace/rfnoc/src/uhd-fpga/usrp3/lib/ > rfnoc/noc_block_fft_tb$ > > make xsim > > BUILDER: Checking tools... > > * GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu) > > * Python 2.7.12 > > * ERROR: Vivado not found in environment. Please run setupenv.sh > > /home/tienvh/workspace/rfnoc/src/uhd-fpga/usrp3/top/../ > tools/make/viv_preamble.mak:47: > > recipe for target '.check_tool' failed > > make: *** [.check_tool] Error 1 > > Which branch are you on, and which version of Vivado do you have installed? > > -- M > > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP
On 01/30/2018 08:08 AM, Dang tien Vo-Huu via USRP-users wrote: > Hi Jonathon, > Thank you for the hint. Actually your suggestion was the first thing I > tried but it didn't work. It threw the error: > > tienvh@gl502vm:~/workspace/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_fft_tb$ > make xsim > BUILDER: Checking tools... > * GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu) > * Python 2.7.12 > * ERROR: Vivado not found in environment. Please run setupenv.sh > /home/tienvh/workspace/rfnoc/src/uhd-fpga/usrp3/top/../tools/make/viv_preamble.mak:47: > recipe for target '.check_tool' failed > make: *** [.check_tool] Error 1 Which branch are you on, and which version of Vivado do you have installed? -- M ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP
Hi Jonathon, Thank you for the hint. Actually your suggestion was the first thing I tried but it didn't work. It threw the error: tienvh@gl502vm:~/workspace/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_fft_tb$ make xsim BUILDER: Checking tools... * GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu) * Python 2.7.12 * ERROR: Vivado not found in environment. Please run setupenv.sh /home/tienvh/workspace/rfnoc/src/uhd-fpga/usrp3/top/../tools/make/viv_preamble.mak:47: recipe for target '.check_tool' failed make: *** [.check_tool] Error 1 Just recently, I've noticed the script build.py locating in uhd-fpga/usrp3/ and I can use it to run the simulation successfully. I guess there are still more useful scripts that I need to explore. Best, Tien On Mon, Jan 29, 2018 at 10:44 PM, Jon Pendlum wrote: > Hi Tien, > > Run 'make xsim' in the same directory as the testbench. > > Jonathon > > On Jan 22, 2018 12:52 PM, "Dang tien Vo-Huu via USRP-users" < > usrp-users@lists.ettus.com> wrote: > > Hi EJ, > It works! Now I am able to simulate the custom block with IP in both > cases. Just another small question, can we simulate the built-in RFNoC > block? I see the simulate file (for example noc_block_fft_tb.sv) but not > sure how to run it.. > Thank you very much for the help. > > Best, > Tien > > > On Mon, Jan 22, 2018 at 10:55 AM, EJ Kreinar wrote: > >> Hi Tien, >> >> If the Xilinx IP is included in the uhd-fpga/usrp3/lib repo, you can >> follow the example provided in the Makefile for the noc_block_fft_tb: >> https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/rfnoc/n >> oc_block_fft_tb/Makefile >> >> Note the three steps: >> 1. set LIB_IP_DIR >> 2. Include the Makefile.inc associated with the Xilinx IP >> 3. Append generated IP to the DESIGN_SRCS >> >> If the Xilinx IP you want to use is contained in an OOT repo, then you >> would want to follow the Makefile.inc process of including the OOT repo: >> https://github.com/ejk43/rfnoc-ootexample >> >> The "noc_block_complextomagphase_tb" example shows an example of how to >> include and simulate Xilinx IP inside an OOT repo: >> https://github.com/ejk43/rfnoc-ootexample/blob/master/ >> rfnoc/testbenches/noc_block_complextomagphase_tb/Makefile >> >> For another example, this repo with a polyphase channelizer also shows >> how to include and simulate Xilinx IP in an OOT repo: >> https://github.com/e33b1711/rfnoc-ppchan >> >> Hope this helps, >> EJ >> >> On Fri, Jan 19, 2018 at 10:28 PM, Dang tien Vo-Huu via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >>> Hi all, >>> I have this error when trying to simulate a custom RFNoC block in an OOT >>> module: >>> >>> $ make noc_block_hbFilter_tb >>> . >>> . >>> Starting static elaboration >>> ERROR: [VRFC 10-2063] Module not found while processing >>> module instance [/home/tienvh/workspace/rfnoc/ >>> src/rfnoc-filters/rfnoc/fpga-src/noc_block_hbFilter.v:179] >>> ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design >>> unit(s) in library work failed. >>> INFO: [USF-XSim-99] Step results log file:'/home/tienvh/workspace/r >>> fnoc/src/rfnoc-filters/rfnoc/testbenches/noc_block_hbFilter_ >>> tb/xsim_proj/xsim_proj.sim/sim_1/behav/elaborate.log' >>> ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check >>> the Tcl console output or '/home/tienvh/workspace/rfnoc/ >>> src/rfnoc-filters/rfnoc/testbenches/noc_block_hbFilter_tb/xs >>> im_proj/xsim_proj.sim/sim_1/behav/elaborate.log' file for more >>> information. >>> . >>> . >>> >>> I can build an FPGA image with the custom RFNoC block following the >>> instruction here: http://www.synchronouslabs.com/blog/creating-a-custom- >>> rfnoc-block-with-using-xillinx-ip >>> but I haven't found a way to simulate this block. >>> Is there any way to run the simulation in this situation? Otherwise it >>> would be difficult to debug if anything goes wrong.. >>> >>> Thanks in advance. >>> >>> Best, >>> Tien >>> >>> ___ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>> >> > > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP
Hi Tien, Run 'make xsim' in the same directory as the testbench. Jonathon On Jan 22, 2018 12:52 PM, "Dang tien Vo-Huu via USRP-users" < usrp-users@lists.ettus.com> wrote: Hi EJ, It works! Now I am able to simulate the custom block with IP in both cases. Just another small question, can we simulate the built-in RFNoC block? I see the simulate file (for example noc_block_fft_tb.sv) but not sure how to run it.. Thank you very much for the help. Best, Tien On Mon, Jan 22, 2018 at 10:55 AM, EJ Kreinar wrote: > Hi Tien, > > If the Xilinx IP is included in the uhd-fpga/usrp3/lib repo, you can > follow the example provided in the Makefile for the noc_block_fft_tb: > https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/rfnoc/n > oc_block_fft_tb/Makefile > > Note the three steps: > 1. set LIB_IP_DIR > 2. Include the Makefile.inc associated with the Xilinx IP > 3. Append generated IP to the DESIGN_SRCS > > If the Xilinx IP you want to use is contained in an OOT repo, then you > would want to follow the Makefile.inc process of including the OOT repo: > https://github.com/ejk43/rfnoc-ootexample > > The "noc_block_complextomagphase_tb" example shows an example of how to > include and simulate Xilinx IP inside an OOT repo: > https://github.com/ejk43/rfnoc-ootexample/blob/master/ > rfnoc/testbenches/noc_block_complextomagphase_tb/Makefile > > For another example, this repo with a polyphase channelizer also shows how > to include and simulate Xilinx IP in an OOT repo: https://github.com/e33b1 > 711/rfnoc-ppchan > > Hope this helps, > EJ > > On Fri, Jan 19, 2018 at 10:28 PM, Dang tien Vo-Huu via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi all, >> I have this error when trying to simulate a custom RFNoC block in an OOT >> module: >> >> $ make noc_block_hbFilter_tb >> . >> . >> Starting static elaboration >> ERROR: [VRFC 10-2063] Module not found while processing >> module instance [/home/tienvh/workspace/rfnoc/ >> src/rfnoc-filters/rfnoc/fpga-src/noc_block_hbFilter.v:179] >> ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design >> unit(s) in library work failed. >> INFO: [USF-XSim-99] Step results log file:'/home/tienvh/workspace/r >> fnoc/src/rfnoc-filters/rfnoc/testbenches/noc_block_hbFilter_ >> tb/xsim_proj/xsim_proj.sim/sim_1/behav/elaborate.log' >> ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check >> the Tcl console output or '/home/tienvh/workspace/rfnoc/ >> src/rfnoc-filters/rfnoc/testbenches/noc_block_hbFilter_tb/xs >> im_proj/xsim_proj.sim/sim_1/behav/elaborate.log' file for more >> information. >> . >> . >> >> I can build an FPGA image with the custom RFNoC block following the >> instruction here: http://www.synchronouslabs.com/blog/creating-a-custom- >> rfnoc-block-with-using-xillinx-ip >> but I haven't found a way to simulate this block. >> Is there any way to run the simulation in this situation? Otherwise it >> would be difficult to debug if anything goes wrong.. >> >> Thanks in advance. >> >> Best, >> Tien >> >> ___ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP
Hi EJ, It works! Now I am able to simulate the custom block with IP in both cases. Just another small question, can we simulate the built-in RFNoC block? I see the simulate file (for example noc_block_fft_tb.sv) but not sure how to run it.. Thank you very much for the help. Best, Tien On Mon, Jan 22, 2018 at 10:55 AM, EJ Kreinar wrote: > Hi Tien, > > If the Xilinx IP is included in the uhd-fpga/usrp3/lib repo, you can > follow the example provided in the Makefile for the noc_block_fft_tb: > https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/rfnoc/ > noc_block_fft_tb/Makefile > > Note the three steps: > 1. set LIB_IP_DIR > 2. Include the Makefile.inc associated with the Xilinx IP > 3. Append generated IP to the DESIGN_SRCS > > If the Xilinx IP you want to use is contained in an OOT repo, then you > would want to follow the Makefile.inc process of including the OOT repo: > https://github.com/ejk43/rfnoc-ootexample > > The "noc_block_complextomagphase_tb" example shows an example of how to > include and simulate Xilinx IP inside an OOT repo: > https://github.com/ejk43/rfnoc-ootexample/blob/master/ > rfnoc/testbenches/noc_block_complextomagphase_tb/Makefile > > For another example, this repo with a polyphase channelizer also shows how > to include and simulate Xilinx IP in an OOT repo: https://github.com/e33b1 > 711/rfnoc-ppchan > > Hope this helps, > EJ > > On Fri, Jan 19, 2018 at 10:28 PM, Dang tien Vo-Huu via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi all, >> I have this error when trying to simulate a custom RFNoC block in an OOT >> module: >> >> $ make noc_block_hbFilter_tb >> . >> . >> Starting static elaboration >> ERROR: [VRFC 10-2063] Module not found while processing >> module instance [/home/tienvh/workspace/rfnoc/ >> src/rfnoc-filters/rfnoc/fpga-src/noc_block_hbFilter.v:179] >> ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design >> unit(s) in library work failed. >> INFO: [USF-XSim-99] Step results log file:'/home/tienvh/workspace/r >> fnoc/src/rfnoc-filters/rfnoc/testbenches/noc_block_hbFilter_ >> tb/xsim_proj/xsim_proj.sim/sim_1/behav/elaborate.log' >> ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check >> the Tcl console output or '/home/tienvh/workspace/rfnoc/ >> src/rfnoc-filters/rfnoc/testbenches/noc_block_hbFilter_tb/xs >> im_proj/xsim_proj.sim/sim_1/behav/elaborate.log' file for more >> information. >> . >> . >> >> I can build an FPGA image with the custom RFNoC block following the >> instruction here: http://www.synchronouslabs.com/blog/creating-a-custom- >> rfnoc-block-with-using-xillinx-ip >> but I haven't found a way to simulate this block. >> Is there any way to run the simulation in this situation? Otherwise it >> would be difficult to debug if anything goes wrong.. >> >> Thanks in advance. >> >> Best, >> Tien >> >> ___ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Re: [USRP-users] x310 simulating RFNoC block with Xilinx IP
Hi Tien, If the Xilinx IP is included in the uhd-fpga/usrp3/lib repo, you can follow the example provided in the Makefile for the noc_block_fft_tb: https:// github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/ rfnoc/noc_block_fft_tb/Makefile Note the three steps: 1. set LIB_IP_DIR 2. Include the Makefile.inc associated with the Xilinx IP 3. Append generated IP to the DESIGN_SRCS If the Xilinx IP you want to use is contained in an OOT repo, then you would want to follow the Makefile.inc process of including the OOT repo: https://github.com/ejk43/rfnoc-ootexample The "noc_block_complextomagphase_tb" example shows an example of how to include and simulate Xilinx IP inside an OOT repo: https://github.com/ ejk43/rfnoc-ootexample/blob/master/rfnoc/testbenches/noc_ block_complextomagphase_tb/Makefile For another example, this repo with a polyphase channelizer also shows how to include and simulate Xilinx IP in an OOT repo: https://github.com/ e33b1711/rfnoc-ppchan Hope this helps, EJ On Fri, Jan 19, 2018 at 10:28 PM, Dang tien Vo-Huu via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi all, > I have this error when trying to simulate a custom RFNoC block in an OOT > module: > > $ make noc_block_hbFilter_tb > . > . > Starting static elaboration > ERROR: [VRFC 10-2063] Module not found while processing > module instance [/home/tienvh/workspace/rfnoc/ > src/rfnoc-filters/rfnoc/fpga-src/noc_block_hbFilter.v:179] > ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design > unit(s) in library work failed. > INFO: [USF-XSim-99] Step results log file:'/home/tienvh/workspace/r > fnoc/src/rfnoc-filters/rfnoc/testbenches/noc_block_hbFilter_ > tb/xsim_proj/xsim_proj.sim/sim_1/behav/elaborate.log' > ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check > the Tcl console output or '/home/tienvh/workspace/rfnoc/ > src/rfnoc-filters/rfnoc/testbenches/noc_block_hbFilter_tb/ > xsim_proj/xsim_proj.sim/sim_1/behav/elaborate.log' file for more > information. > . > . > > I can build an FPGA image with the custom RFNoC block following the > instruction here: http://www.synchronouslabs.com/blog/creating-a-custom- > rfnoc-block-with-using-xillinx-ip > but I haven't found a way to simulate this block. > Is there any way to run the simulation in this situation? Otherwise it > would be difficult to debug if anything goes wrong.. > > Thanks in advance. > > Best, > Tien > > ___ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > ___ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
