This issue should now be fixed in trunk.
On Sun, Oct 21, 2012 at 11:16 AM, Avinash Malik ama...@scss.tcd.ie wrote:
Hello,
I tried compiling the running X10 GPU examples provided in the
x10-trunk/x10.dist/samples/CUDA directory without success.
The error I get is:
Thanks for your reports, I can actually reproduce this, it looks like a
regression in the last release. We'll try and fix it in trunk asap.
On Mon, Dec 10, 2012 at 3:50 PM, Paul Osmialowski newch...@king.net.plwrote:
Hello,
I'm new here and I just heard about x10 language, although I'm
Hi
You are correct, in X10 those critical sections would be unnecessarily
serialised. Only one lock is used per place, and each atomic section will
contend on that one lock.
If this causes a problem, you can use explicit locks (just like Java), or
you can use or write a lock-free datastructure.
'.
On Feb 13, 2012, at 6:23 PM, Dave Cunningham wrote:
I would guess you are right, they have probably broken backwards
compatability in that version. I'll need to get the latest CUDA installed
and try it. In the mean time, can you paste the output of nvcc --help on
your system, at this point
I would guess you are right, they have probably broken backwards
compatability in that version. I'll need to get the latest CUDA installed
and try it. In the mean time, can you paste the output of nvcc --help on
your system, at this point:
--gpu-architecture gpu architecture name (-arch)
[...]
:)
Cheers :)
Richard Gomes
http://www.jquantlib.org/index.php/User:RichardGomes
twitter: frgomes
JQuantLib is a library for Quantitative Finance written in Java.
http://www.jquantlib.com/
twitter: jquantlib
On 28/02/11 07:52, Dave Cunningham wrote:
I was able to reproduce
I was able to reproduce this and got this trace from valgrind but I'm on
vacation for a week so cannot debug further
==23823== Invalid read of size 1
==23823==at 0x4027411: memcpy (mc_replace_strmem.c:497)
==23823==by 0x80CD8F3: x10aux::deserialization_buffer::Readunsigned
No. It is still an open question how best to implement atomic and when in
X10.
The spec allows weak atomicity, so many avenues are open.
The current implementation is 1 lock per place.
On Fri, Feb 11, 2011 at 10:54 AM, Aditya Sriram M
aditya.mattapar...@iiitb.org wrote:
Hi,
Does X10
I don't know if -DX10RT_CUDA is sufficient as I always do -DX10RT_CUDA=true
I don't know why it can't find x10aux/config.h, the nvcc options must be
wrong. Can you run x10c++ with -report postcompile=5 and show the nvcc
line?
How come you were able to run it if it failed compile?
By the way
You can pass structs as parameters to native functions, or even define your
own struct natively. If you tell us the precise API you want, we can
probably point you to some existing code that you can use as a template.
If in doubt, check the c++ code emitted by x10c++ :)
On Thu, Jan 20, 2011 at
I think the problem is you are using mpirun with the sockets backend. Try
this:
X10_NPLACES=4 ./sw -s data/short9.txt -l data/long9.txt -p
To use mpirun you have to compile X10 for MPI, the binary downloads do not
support it.
On Tue, Jan 18, 2011 at 7:23 AM, David P Grove gro...@us.ibm.com
Try setting X10_NTHREADS=1
MPI implementations have been known to play games with thread affinity
On Mon, Dec 20, 2010 at 3:42 PM, Benjamin W Herta bhe...@us.ibm.com wrote:
It's normal for idle places to use CPU - it's constantly checking the
network for incoming messages. This helps
I thought this was made into an environment variable at some point but can't
see it in the code.
You can change this and recompile
x10.runtime/x10rt/standalone
#define X10RT_DATABUFFERSIZE 524300 // the size, in bytes, of the shared
memory segment used for communications, per place
Or you can
This would form part of the database of useful info at each place I think.
Something like a Map[String,Any] where if there was no IPAddress then it
would simply return null. Other stuff that needs to go into the db includes
number of cores, other places on the same host, children places, and
Might be outdated by now, but I vaguely remember that I was told in May
that there is another corner case worth mentioning: In case the atomic block
works on a single integer for instance, then it is compiled down to
something like compare-and-swap, sidestepping the global lock, no?
That
Executing this example I've got the following message
X10RT: async 37 is not a CUDA kernel.
If I'm not wrong, this message comes from the kernel function, once this
message dissapears when I comment out the call to the kernel function.
I suspect the kernel activity is getting
On Tue, Dec 7, 2010 at 9:45 AM, Claudia Fohry fo...@uni-kassel.de wrote:
Hi,
according to the standard (p. 163), atomic is executed as if in a single
step
during which all other concurrent activities in the same place are
blocked.
This is just a description of its behaviour. There are
Try Y-set(get_val(), 1)
On Thu, Dec 2, 2010 at 1:55 PM, Kirak Hong hok...@gatech.edu wrote:
Hi,
*
*Does anyone know how to access X10 Array in the native code block?
I am trying to copy a whole matrix (array with rank 2) from C++ to X10, but
I couldn't even access one element of X10 array
I believe C++ calls fields 'member variables'
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If you're using the c++ backend then, depending on the error, the g++
version is sometimes useful.
On Tue, Nov 23, 2010 at 10:18 AM, Christoph Pospiech
christoph.pospi...@de.ibm.com wrote:
Hi,
my little X10 program drove X10 2.1 into a compiler internal error. Do you
want me to open a JIRA
Hi
The error message doesn't necessarily imply that nvcc couldn't be found, in
fact the errors you got were from nvcc, and we print the same message no
matter how the invocation of nvcc fails.
The problem was a regression caused by a recent change in SVN, it's now
fixed in r18467
thanks for
Yeah it used to live in the directory below, you could also copy up the
points.dat from there.
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A team is used to identify the participants of a collective operation. See
the documentation on collective operations here:
http://dist.codehaus.org/x10/x10rt/x10rt__front_8h.html
On Tue, Nov 23, 2010 at 5:08 PM, Jeeva Paudel je...@ualberta.ca wrote:
Hi,
In the X10RT API, there is a
finish async at (c) @CUDA @CUDADirectParams {
gmemory(0) = CUDAUtilities.autoBlocks();// line 57
gmemory(1) = CUDAUtilities.autoThreads();
}
You need the rest of the kernel too. There are no blocks / threads loops,
no shared memory definitions, and no
,
Could you please send the patch again?
Thanks
Richard Gomes
M: +44(77)9955-6813
http://tinyurl.com/frgomes
twitter: frgomes
JQuantLib is a library for Quantitative Finance written in Java.
http://www.jquantlib.org/
twitter: jquantlib
On 09/11/10 03:45, Dave Cunningham
Forgot to mention, you can work around the segfault by commenting out any
calls to CUDAUtilities.deleteRemoteArray
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Thanks for trying out X10/CUDA
Your initial problem with CUDATopology is due to the fact that X10RT_ACCELS
is ineffective if X10 was built without -DX10RT_CUDA=true, this means the
X10 application was unable to 'see' the accelerators. You correctly
surmised that building X10 from the source
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