From: Andrii Anisov
This reduces some code and conditions in an IRQ processing path,
reducing IRQ latency for a build supported GICV2 only.
Signed-off-by: Andrii Anisov
---
Its a patch [1] with a better message and removed build errors.
Comments from Andre are not addressed yet.
[1] https
From: Andrii Anisov
This function is called under IRQs disabled already, so drop additional
flags save and restore.
Signed-off-by: Andrii Anisov
---
This patch is a part of [1] and already sent to the list [2].
[1] https://lists.xenproject.org/archives/html/xen-devel/2018-11/msg03293.html
[2
From: Andrii Anisov
Simplify context restore from idle vcpu to the one ran before it.
This improves low cpu load but high irq rate use-cases.
Signed-off-by: Andrii Anisov
---
xen/arch/arm/domain.c | 21 +++--
xen/include/xen/sched.h | 1 +
2 files changed, 12 insertions
justification commit message]
Signed-off-by: Andrii Anisov
---
xen/arch/arm/arm64/entry.S | 11 +--
xen/arch/arm/traps.c | 6 ++
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/xen/arch/arm/arm64/entry.S b/xen/arch/arm/arm64/entry.S
index 97b05f5..8f28789 100644
--- a
From: Andrii Anisov
Because the HCR value is only changed by the hypervisor,
we can rely on a cached value and do not do peripheral register
reads for this register.
Signed-off-by: Andrii Anisov
---
xen/arch/arm/gic-v2.c | 43 +--
xen/arch/arm/gic
From: Andrii Anisov
Avoid excessive conversions between `pending_irq` and irq number and
priority. This is a tiny but pure optimization.
Also it aligns a `gic_raise_guest_irq()` function interface to its
current implementation in the meaning that it is removed a clearly
ignored priority
From: Andrii Anisov
For GICV2 pending_irq allocation is not concurrent, so reduce
some code under lock.
This code is not supposed to work with GICv3
Signed-off-by: Andrii Anisov
---
xen/arch/arm/gic-v3-its.c | 2 ++
xen/arch/arm/gic-v3-lpi.c | 2 ++
xen/arch/arm/gic-v3.c | 2 ++
xen/arch
From: Andrii Anisov
After the patch "xen/arm: Re-enable interrupt later in the trap path"
this function is called with irqs already locked.
Signed-off-by: Andrii Anisov
---
xen/arch/arm/gic-vgic.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/xen/ar
From: Andrii Anisov
This saves one write to peripheral HCR register per hypervisor entry for
most cases.
Signed-off-by: Andrii Anisov
---
xen/arch/arm/gic-v2.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index
From: Andrii Anisov
All bit operations for gic, vgic and gic-vgic are performed under
spinlocks, so there is no need for atomic bit ops here, they only
introduce excessive call to functions used more expensive exclusive
ARM instructions.
Signed-off-by: Andrii Anisov
---
This patch was not
From: Andrii Anisov
Do not put already disabled IRQs into any of queues, and remove
an IRQ from all queues on disable. Insert the IRQ into queues on
enable if needed. This also allows simplification of under-lock
decission of events needed delivery.
Signed-off-by: Andrii Anisov
---
xen/arch
From: Andrii Anisov
This patch series is an attempt to reduce IRQ latency with the
old GIC implementation (gic-vgic). These patches originally based
on XEN 4.10 release. The motivation was to improve benchmark
results of a system given to a customer for evaluation.
This patch series is tailored
From: Andrii Anisov
Pause_flags is not related to vgic spinlock, so reduce code
under lock.
Signed-off-by: Andrii Anisov
---
Comments from Julien [1] are not addressed yet.
[1] https://lists.xenproject.org/archives/html/xen-devel/2018-11/msg03306.html
---
xen/arch/arm/vgic.c | 13
From: Andrii Anisov
Cache line size assumed 64 byte as for H3. Align the `struct
pending_irq` and allocate lrs shadow aligned to cache line size.
Signed-off-by: Andrii Anisov
---
xen/arch/arm/domain.c| 4
xen/arch/arm/vgic.c | 9 +
xen/include/asm-arm/config.h
Hello Jairo,
From: LOPEZ, FUENTES NACARINO Jairo Eduardo
Sent: Saturday, December 22, 2018 3:55 AM
To: Andrii Anisov; Iurii Artemenko
Subject: RT Xen on ARM - R-Car series
> My name is Jairo Lopez.
> I am currently working as a doctorate student at Waseda University in the
>
From: Andrii Anisov
This function is called under IRQs disabled already, so drop additional
flags save and restore.
Signed-off-by: Andrii Anisov
---
This is a half of an RFC patch [1] which relies on the already
existing code.
[1] https://lists.xenproject.org/archives/html/xen-devel/2018-11
From: Andrii Anisov
This function is called under IRQs disabled already, so drop additional
flags save and restore.
Signed-off-by: Andrii Anisov
---
This is a half of an RFC patch [1] which relies on the already
existing code.
[1] https://lists.xenproject.org/archives/html/xen-devel/2018-11
From: Andrii Anisov
This reduces the number of context switches in case we have coming guest
interrupts from different sources at a high rate. What is likely for
multimedia use-cases.
Having irqs unlocked here makes us go through trap path again in case we
have a new guest interrupt arrived
On 21.12.18 19:27, Julien Grall wrote:
Is it a wildcard tag? :)
No, just a wrong copy-paste.
Must be:
Reviewed-by: Andrii Anisov
;)
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https
Reviewed-by: Andrii Anisov
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
-only foreign mappings. For now,
the decision between the two foreign mapping type is based on the type
of the guest page mapped.
Signed-off-by: Julien Grall
Andrii Anisov
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel
want to provide "non-auto translated helpers" in the future if we
see more case.
Signed-off-by: Julien Grall
Andrii Anisov
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.o
current VMID.
The workaround implemented in Xen will:
- Use an empty stage-2 with a reserved VMID while context switching
between 2 guests
- Use an empty stage-2 with the VMID where TLBs need to be flushed
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
--
Sincerely,
Andrii
I've missed that this patch is already merged within a different series.
Also "[Xen-devel] [PATCH for-4.12 6/8] xen/arm: Implement workaround for Cortex-A76
erratum 1165522" should be rebased.
On 21.12.18 16:44, Andrii Anisov wrote:
On 28.11.18 18:49, Julien Grall wrote
) to use a guest PA.
This will also help a follow-up patch which will require
p2m_{save,restore}_state to work in pair to workaround an erratum.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailin
On 21.12.18 16:47, Andrew Cooper wrote:
On 21/12/2018 14:44, Andrii Anisov wrote:
I guess this one should not be here.
Posting patches like this can be useful for people trying to test the
series.
As such, it is worth posting, but the DO NOT APPLY hint is there for
people to realise that
I guess this one should not be here.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
On 28.11.18 18:49, Julien Grall wrote:
A lot of the headers are not necessary, so remove them. At the same
time, re-order them alphabetically.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
--
Sincerely,
Andrii Anisov.
___
Xen-devel
On 28.11.18 18:49, Julien Grall wrote:
if ( *last_vcpu_ran != INVALID_VCPU_ID && *last_vcpu_ran != n->vcpu_id )
+{
flush_tlb_local();
+}
BTW, missed mentioning that curly braces above are odd by coding style.
--
Sincerely,
An
returning to the guest (exception returns will synchronized the
context).
Remove unecessary isb() and document the ones left.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel
On 28.11.18 18:49, Julien Grall wrote:
A follow-up patch will require to allocate the root page-table without
having a domain in hand.
Signed-off-by: Julien Grall
Reviewed-by: Andrii Anisov
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing
On 28.11.18 18:49, Julien Grall wrote:
A follow-up patch will need to generate the VTTBR in a few places.
Signed-off-by: Julien Grall
---
xen/arch/arm/p2m.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
Reviewed-by: Andrii Anisov
--
Sincerely,
Andrii Anisov
(+), 2 deletions(-)
Reviewed-by: Andrii Anisov
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
Reviewed-by: Andrii Anisov
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
for one 10 line function is really
useful.
So that was the best solution. I am open to other suggestion.
Cheers,
Reviewed-by: Andrii Anisov
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproj
Andre,
Could you please comment on the patch and below.
On 20.11.18 13:09, Andrii Anisov wrote:
Hello Andre,
I'm going to change "gic_raise_guest_irq()" function interface.
Could you please comment my understanding of vgic-v3-its.c code below? So that
I could fix it alongsi
hat the break-before-make issue is not fixed by this patch.
Signed-off-by: Julien Grall
Reported-by: Matthew Daley
Tested-by: Matthew Daley
As long as the code did not change:
Tested-by: Andrii Anisov
Reviewed-by: Andrii Anisov
--
Sincerely,
Andrii Ani
Hello Julien,
On 17.12.18 19:34, Andrii Anisov wrote:
I see something like following as a quick WA (not even build tested):
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index d2c63a8..bf72ba9 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
n't want format this as PRIpaddr (16 digit hex) */
(unsigned long)(kinfo->unassigned_mem >> 20));
But I'm not sure if it worth to be sent, because I'm going to rewrite it soon.
--
Sincerely,
Andrii Anisov.
_
already noticed I've passed my RB and TB for the patch.
I would prefer you reflect last findings in the commit message, but if you
don't like - let it be as is.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject
ed int min_low_order =
get_order_from_bytes(min_t(paddr_t, dom0_mem, MB(128)));
in `allocate_memory_11()` prone to end up with a wrong RAM start alignment.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.
On 14.12.18 20:04, Julien Grall wrote:
Then the code needs to be fixed... It would be nice to get some helps here as I
can't scale.
I can take this.
But I would like to align on the algorithm first.
--
Sincerely,
Andrii Anisov.
___
Xen-
urce/Documentation/arm/Booting#L160
[1] Documentation/arm/Booting
[2] Documentation/arm64/booting.txt
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
the case
then there is a bug in Xen that should be fixed.
They are stolen from 1:1 memory allocation because of `allocate_memory_11()`
design and implementation.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
h
128MB aligned.
Look at `allocate_memory_11()`, `min_low_order` variable usage. It affects all
low memory 1:1 allocation and makes all low memory banks 128MB aligned both
start and end.
So that having a module in a low memory poisons the whole 128MB region.
--
Sincerely,
Andrii A
ew Daley
Tested-by: Matthew Daley
Tested-by: Andrii Anisov
Reviewed-by: Andrii Anisov
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
On 14.12.18 17:52, Andrii Anisov wrote:
Hello Julien,
Let me speculate a bit about the topic.
On 14.12.18 13:44, Julien Grall wrote:
At the moment, Xen is relocated towards the end of the memory.
This statement is not really true. Some time ago, XEN was relocated toward the
end of
the low
setup, we do not care about Dom0 and its 1:1 mapped memory. And,
all in all, we have an IOMMU.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
version.
I noticed that when received the series back from the list.
Sorry for the mess.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
Hello Juergen,
On 13.12.18 18:37, Juergen Gross wrote:
You should use linux kernel commit 3596924a233e45aa918.
That is exactly what is needed.
Thank you!
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https
w
lines below:
balloon_set_new_target(new_target - target_diff);
`balloon_set_new_target()` receives a value wrapped over 64bit what kills the
system.
Now I'm looking for an appropriate kernel patch for the kernel, to fix that.
Any suggestions?
--
Sincerely,
even
without doing the pinning? If yes, can I ask how?
Yeh, it took me some time to recall that from my memory:)
When I tried using xentrace to profile interrupt path, I noticed that `current`
non-idle VCPU is not changed for a particular PCPU.
--
Sincerely,
Andrii Anisov.
_
From: Andrii Anisov
Here are few patches from RFC series [1] currently approved to
be upstreamed with appropriate changes.
Andrii Anisov (2):
gic-vgic: Drop an excessive clear_lrs
Is a patch #5 [2], with a change:
- Keep LR clear for debug build
No changes in v2
From: Andrii Anisov
This action is excessive because for an invalid LR there is no need
to write another invalid value to a register. So we can skip it here,
saving a peripheral register write.
Keep clearing the LR for the DEBUG build. This would make dumped
invalid LRs be zero. That is more
From: Andrii Anisov
Under desc->lock taken:
An IRQ with _IRQ_GUEST flag set always has an action.
An IRQ with _IRQ_DISABLED flag cleared always has an action.
Those flags checks cover all accesses to desc->action in do_IRQ,
so we can skip desc->action check in non-debug build.
Keep in
ntially need to update no_irq_type and EOI "spurious interrupt".
I am not entirely sure which way is the best to address the race. Any opinions?
Let me spend a bit more time to look into that
Other wording and grammatical nits will be
On 12.12.18 19:49, Julien Grall wrote:
Please don't add a reviewed-by tag until it was explicitly written by the
reviewer.
My bad, I mixed it with #5.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
baremetal numbers in hyp mode.
Did you try my RFC on your HW?
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
tice, there is. :-)
I know it very well :)
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
From: Andrii Anisov
Here are few patches from RFC series [1] currently approved to
be upstreamed with appropriate changes.
Andrii Anisov (2):
gic-vgic: Drop an excessive clear_lrs
Is a patch #5 [2], with a change:
- Keep LR clear for debug build
arm/irq: skip action
From: Andrii Anisov
This action is excessive because for an invalid LR there is no need
to write another invalid value to a register. So we can skip it here,
saving a peripheral register write.
Keep clearing the LR for the DEBUG build. This would make dumped
invalid LRs be zero. That is more
From: Andrii Anisov
An IRQ with _IRQ_GUEST flag set always has an action.
An IRQ with _IRQ_DISABLED flag cleared always have an action.
Those flags checks cover all accesses to desc->action in do_IRQ,
so we can skip desc->action check.
Still keep it in place for debug build.
Signed-
safe with
`_IRQ_DISABLED` flag when `action` is not set.
So I'll keep the code in its current place (as of mainline) and wrap it with
`#ifndef NDEBUG`.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
debug build without the check.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
&desc->status) )`? One with `#ifndef NDEBUG`, other
without.
Is my understanding correct?
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
e spi path).
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
TBM. Does it fit your vision?
Can you send separately patches I said I am happy with for Xen 4.12? We can
then continue to discuss the others with numbers and see if we can merge them
in time.
Yep.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing
Julien,
Sorry for bothering you too much.
What about this patch?
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
it for 4.12 together with #1?
I plan to send separately patches you have reviewed first. Then evaluate the
rest with TBM. Does it fit your vision?
I would add an ASSERT(!local_is_irq_enabled()) on top to show that this should
be called with interrupt disabled.
OK.
--
Sincerely,
Andrii Anisov
> struct irq_guest *info = irq_get_guest_info(desc);
+ASSERT( desc->action != NULL );
What would you prefer?
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
ction avalability check
for guest's IRQ"?
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
On 12.12.18 11:46, Andrii Anisov wrote:
Digging into that now.
I got it. My u-boot starts TBM in hyp mode. But them both miss setting
HCR_EL2.IMO, so no interrupt exception was taken in hyp.
OK, for my baremetal TBM in hyp, numbers are:
max=840 warm_max=120 min=120 avg=127
I guess, warm_max
being called. But I see the interrupt fired and become active in GIC
registers.
Digging into that now.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
t sort
out the cause yet. And Julien says it is not reproducible on his desk.
But yes, with VCPU number less than PCPUs - there is no migration of Dom0 VCPUs.
[1] https://lists.xenproject.org/archives/html/xen-devel/2018-12/msg00435.html
--
Sincerely
Hello Julien,
On 11.12.18 14:27, Julien Grall wrote:
I would like to have performance per patch so we can make the decisions whether
the implementation cost is worth it for upstream.
I'll check baremetal numbers first. Then will get numbers per patch.
--
Sincerely,
Andrii A
t patch by patch?
No. Not yet.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
] https://lists.xenproject.org/archives/html/xen-devel/2018-11/msg03288.html
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
_Free:0
HugePages_Rsvd:0
HugePages_Surp:0
Hugepagesize: 2048 kB
So that's reliably happening?
It is 100% reproducible on my setup.
Are you sure there are nothing else on the system using memory? For instance
you seem to have nfs in place.
Yes, Dom0 root is nfs.
emons, Xen daemons, other Yocto daemons. Actually, nothing
special.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
pp in different
use-cases, bringing it up with new vgic.
How much work did you do on the platform before triggering oem-killer?
Without cpu pinning I do all I need without oom-killer being triggered.
After cpu pinning it takes 5-10 seconds until oom-killer starts to kill
everything.
--
Sincerely,
A
. I'm trying to measure IRQ latency as
Stefano did.
How much memory do you have in Dom0? Do you have any memory hungry process
running?
Dom0 has 3Gb RAM. But it's not about the memory, I'm pretty sure. Until I
decided to pin vcpus, I did all my routine without any issues.
It happens with credit and credit2 schedulers, with old and new vgic.
On 05.12.18 12:26, Andrii Anisov wrote:
Hello,
On the current
6d8ffac (xenbits/master) xen/arm: gic: Remove duplicated comment in do_sgi
and
7073942 (xenbits/staging, xenbits/smoke, xenbits/coverity-tested/smoke
), nodemask=(null), order=0,
oom_score_adj=0
[ 45.867983] systemd cpuset=/ mems_allowed=0
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
ave
multimedia scenarios on the table.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
27;ve used it recently for this theme.
But it gave me unclear results, I did not match them with what I got
from xentrace and rough lauterbach traces.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
th it. If you can provide number that shows
you can improve performance by more than 10% in common case with this
patch only, then I will reconsider my position.
I got it.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-
is not required in a guest interrupt processing path.
--
Sincerely,
Andrii Anisov.
___
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
o with the Linux way
of using __set_bit to provide a non-atomic version?
This would have the big advantage that you can replace them on a
case-by-case base, which is much less risky than unconditionally
replacing every (even future!) usage in the whole file.
Whatever you prefer :)
--
Sinc
-> EOI
-> DIR
Guest IRQ:
-> read_irq
-> local_irq_enable
As I understand, the line above should not be there.
-> do_IRQ
-> EOI
-> vgic_inject_irq
SGIs seems to be handled with IRQ disabled, so no change there.
x27;m pretty scared of new vgic locking scheme with per-irq locks and
locking logic i.e. in vgic_queue_irq_unlock() function. Also sorting
list in vgic_flush_lr_state() with vgic_irq_cmp() looks very expensive.
But, for sure all that stuff performance shou
SoC
specific, so going to take it in use.
The numbers have improved now thanks to vwfi=native and other
optimizations but the mechanism to setup the experiment are the same.I know
about `vwfi=native` but it does not fit our requirements :(
--
Sincerely,
Andrii An
Hello,
Again, I sent this cover letter only to myself. So, here it is, hope it does
not break the thread. Sorry for the mess.
From: Andrii Anisov
Sent: Wednesday, November 28, 2018 11:31 PM
Cc: Andrii Anisov
Subject: [RFC 00/16] Old GIC (gic-vgic) optimizations for GICV2
From: Andrii
From: Andrii Anisov
PPI are pcpu private, so their processing is not concurrent and do not
need pcpu shared flags and correspondent lockings. So avoid odd bits
sets, checks and locks.
Signed-off-by: Andrii Anisov
---
xen/arch/arm/gic.c| 8 ++--
xen/arch/arm/irq.c| 32
From: Andrii Anisov
Those fucntions are called under IRQs disabled already, so avoid
additional flags saving and restore.
Signed-off-by: Andrii Anisov
---
xen/arch/arm/gic-vgic.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/xen/arch/arm/gic-vgic.c b/xen/arch
From: Andrii Anisov
This saves one write to peripheral HCR register per hypervisor entry for
most cases.
Signed-off-by: Andrii Anisov
---
xen/arch/arm/gic-v2.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index
From: Andrii Anisov
Pause_flags is not related to vgic spinlock, so reduce code
under lock.
Signed-off-by: Andrii Anisov
---
xen/arch/arm/vgic.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index a2419d0..a64633f
From: Andrii Anisov
Do not put already disabled IRQs into any of queues, and remove
an IRQ from all queues on disable. Insert the IRQ into queues on
enable if needed. This also allows simplification of under-lock
decission of events needed delivery.
Signed-off-by: Andrii Anisov
---
xen/arch
From: Andrii Anisov
All bit operations for gic, vgic and gic-vgic are performed under
spinlocks, so there is no need for atomic bit ops here, they only
introduce excessive call to functions used more expensive exclusive
ARM instructions.
Signed-off-by: Andrii Anisov
---
xen/arch/arm/gic
From: Andrii Anisov
Simplify context restore from idle vcpu to the one ran before it.
This improves low cpu load but high irq rate use-cases.
Signed-off-by: Andrii Anisov
---
xen/arch/arm/domain.c | 21 +++--
xen/include/xen/sched.h | 1 +
2 files changed, 12 insertions
From: Andrii Anisov
Cache line size assumed 64 byte as for H3. Align the `struct
pending_irq` and allocate lrs shadow aligned to cache line size.
Signed-off-by: Andrii Anisov
---
xen/arch/arm/domain.c| 4
xen/arch/arm/vgic.c | 9 +
xen/include/asm-arm/config.h
301 - 400 of 565 matches
Mail list logo
