> From: Jan Beulich
> Sent: Friday, March 15, 2024 12:23 AM
>
> We'd like to thank Kevin, so far the VT-d maintainer, for his past
> contributions, while at the same time we'd like to reflect reality as it
> has been for quite some time. Have VT-d maintainership (and for symmetry
> also AMD
> From: Jan Beulich
> Sent: Monday, March 4, 2024 5:28 PM
>
> We'd like to thank the VT-x maintainers for their past contributions,
> while at the same time we'd like to reflect reality as it has been for
> quite some time. Have VT-x maintainership (and for symmetry also AMD
> SVM's) fall back
> From: Andrew Cooper
> Sent: Thursday, April 6, 2023 5:53 AM
>
> At the time of XSA-170, the x86 instruction emulator was genuinely broken.
> It
> would load arbitrary values into %rip and putting a check here probably was
> the best stopgap security fix. It should have been reverted following
> From: Jan Beulich
> Sent: Wednesday, August 16, 2023 5:52 PM
>
> Old gcc won't cope with initializers involving unnamed struct/union
> fields.
>
> Fixes: 3e033172b025 ("x86/iommu: pass full IO-APIC RTE for remapping table
> update")
> Signed-off-by: Jan Beulich
>
Reviewed-by: Kevin Tian
> From: Roger Pau Monne
> Sent: Friday, July 28, 2023 5:57 PM
>
> So that the remapping entry can be updated atomically when possible.
>
> Doing such update atomically will avoid Xen having to mask the IO-APIC
> pin prior to performing any interrupt movements (ie: changing the
> destination and
> From: Roger Pau Monne
> Sent: Wednesday, July 26, 2023 8:55 PM
>
> Preparatory change to unify the IO-APIC pin variable name between
> io_apic_read_remap_rte() and amd_iommu_ioapic_update_ire(), so that
> the local variable can be made a function parameter with the same name
> across vendors.
> From: Roger Pau Monne
> Sent: Thursday, May 25, 2023 4:09 PM
>
> Fix two issues related to leaf address lookups in VT-d:
>
> * When translating an address that falls inside of a superpage in the
> IOMMU page tables the fetching of the PTE value wasn't masking of the
> contiguous related
> From: Andrew Cooper
> Sent: Tuesday, May 16, 2023 10:54 PM
>
> MSR_ARCH_CAPS data is now included in featureset information.
>
> Signed-off-by: Andrew Cooper
Reviewed-by: Kevin Tian
> From: Andrew Cooper
> Sent: Thursday, May 11, 2023 3:34 AM
>
> Technically our helper post-dates all of these examples, but it's good cleanup
> nevertheless. None of these examples should be using fully locked
> test_and_set_bool() in the first place.
>
> No functional change.
>
>
> From: Jan Beulich
> Sent: Wednesday, April 26, 2023 8:58 PM
>
> When either feature is available in hardware, but disabled for a guest,
> the respective insn would better cause #UD if attempted to be used.
>
> Signed-off-by: Jan Beulich
>
Reviewed-by: Kevin Tian
> From: Jan Beulich
> Sent: Wednesday, April 26, 2023 8:58 PM
>
> Both have separate enable bits, which are optional. While on real
> hardware we can perhaps expect these VMX controls to be available if
> (and only if) the base CPU feature is available, when running
> virtualized ourselves this
> From: Dmitry Isaykin
> Sent: Tuesday, March 21, 2023 9:59 PM
>
> Adds monitor support for I/O instructions.
>
> Signed-off-by: Dmitry Isaykin
> Signed-off-by: Anton Belousov
Reviewed-by: Kevin Tian
> From: Jan Beulich
> Sent: Friday, March 3, 2023 3:32 PM
>
> Switches of altp2m-s always expect a valid altp2m to be in place (and
> indeed altp2m_vcpu_initialise() sets the active one to be at index 0).
> The compiler, however, cannot know that, and hence it cannot eliminate
>
> From: Marek Marczykowski-Górecki
> Sent: Tuesday, March 14, 2023 9:32 AM
>
> If the scope for IGD's IOMMU contains additional device that doesn't
> actually exist, iommu=no-igfx would not disable that IOMMU. In this
> particular case (Thinkpad x230) it included
> 00:02.1, but there is no such
> From: Jan Beulich
> Sent: Tuesday, February 28, 2023 5:52 PM
>
> Marking a DRHD as controlling an IGD isn't very sensible without
> checking that at the very least it's a graphics device that lives at
> :00:02.0. Re-use the reading of the class-code to control both the
> clearing of
> From: Xenia Ragiadakou
> Sent: Monday, February 13, 2023 7:50 PM
>
> APIC virtualization support is currently implemented only for Intel VT-x.
> To aid future work on separating AMD-V from Intel VT-x code, instead of
> calling directly vmx_vlapic_msr_changed() from common hvm code, add a
>
> From: Jan Beulich
> Sent: Wednesday, February 1, 2023 5:30 PM
>
> On 01.02.2023 06:07, Tian, Kevin wrote:
> >> From: Xenia Ragiadakou
> >> Sent: Tuesday, January 24, 2023 8:42 PM
> >>
> >> The variable untrusted_msi indicates whether th
> From: Xenia Ragiadakou
> Sent: Tuesday, January 24, 2023 8:42 PM
>
> The function hvm_dpci_isairq_eoi() has no dependencies on VT-d driver
> code
> and can be moved from xen/drivers/passthrough/vtd/x86/hvm.c to
> xen/drivers/passthrough/x86/hvm.c, along with the corresponding
> copyrights.
>
> From: Xenia Ragiadakou
> Sent: Tuesday, January 24, 2023 8:42 PM
>
> Posted interrupt support in Xen is currently implemented only for the
> Intel platforms. Instead of calling directly pi_update_irte() from the
> common hvm code, add a pi_update_irte callback to the hvm_function_table.
>
> From: Xenia Ragiadakou
> Sent: Tuesday, January 24, 2023 8:42 PM
>
> The variable untrusted_msi indicates whether the system is vulnerable to
> CVE-2011-1898 due to the absence of interrupt remapping support.
> Although AMD iommus with interrupt remapping disabled are also affected,
> this
> From: Jan Beulich
> Sent: Friday, January 20, 2023 4:44 PM
>
> First of all the variable is meaningful only when an IOMMU is in use for
> a guest. Qualify the check accordingly, like done elsewhere. Furthermore
> the controlling command line option is supposed to take effect on VT-d
> only.
> From: Andrew Cooper
> Sent: Thursday, January 19, 2023 3:37 AM
>
> The original patch tried to do two things - implement VMNotify, and
> re-optimise VT-x to not intercept #DB/#AC by default.
>
> The second part is buggy in multiple ways. Both GDBSX and Introspection
> need
> to conditionally
> From: Andrew Cooper
> Sent: Monday, January 9, 2023 8:08 PM
>
> Ice Lake (server at least) has both Arch LBR and model-specific LBR. Sapphire
> Rapids does not have model-specific LBR at all. I.e. On SPR and later,
> model_specific_lbr will always be NULL, so we must make changes to avoid
>
> From: Andrew Cooper
> Sent: Monday, January 9, 2023 8:08 PM
>
> There is no point repeating this calculation at runtime, especially as it is
> in the fallback path of the WRSMR/RDMSR handlers.
>
> Move the infrastructure higher in vmx.c to avoid forward declarations,
> renaming
> From: Roger Pau Monne
> Sent: Wednesday, December 14, 2022 12:31 AM
>
> Add support for enabling guest Bus Lock Detection on Intel systems.
> Such detection works by triggering a vmexit, which ought to be enough
> of a pause to prevent a guest from abusing of the Bus Lock.
>
> Add an extra
> From: Roger Pau Monne
> Sent: Wednesday, December 14, 2022 12:31 AM
>
> Introduce a small helper to OR VMX_INTR_SHADOW_NMI in
> GUEST_INTERRUPTIBILITY_INFO in order to help dealing with the NMI
> unblocked by IRET case. Replace the existing usage in handling
> EXIT_REASON_EXCEPTION_NMI and
> From: Jan Beulich
> Sent: Monday, October 10, 2022 6:25 PM
>
> With the addition of vmx_add_msr() calls to construct_vmcs() there are
> now cases where simply freeing the VMCS isn't enough: The MSR bitmap
> page as well as one of the MSR area ones (if it's the 2nd vmx_add_msr()
> which fails)
> From: Marczykowski, Marek
> Sent: Tuesday, September 27, 2022 7:54 AM
>
> On Fri, Sep 23, 2022 at 07:21:04AM +, Tian, Kevin wrote:
> > > From: Marek Marczykowski-Górecki
> > > Sent: Saturday, September 17, 2022 10:51 AM
> > >
> > > Re-us
> From: Marek Marczykowski-Górecki
> Sent: Saturday, September 17, 2022 10:51 AM
>
> Re-use rmrr= parameter handling code to handle common device reserved
> memory.
>
> Signed-off-by: Marek Marczykowski-Górecki
>
> ---
> Changes in v3:
> - make MAX_USER_RMRR_PAGES applicable only to
> From: Roger Pau Monne
> Sent: Friday, July 1, 2022 9:17 PM
> @@ -4589,6 +4601,22 @@ void vmx_vmexit_handler(struct cpu_user_regs
> *regs)
> */
> break;
>
> +case EXIT_REASON_NOTIFY:
> +__vmread(EXIT_QUALIFICATION, _qualification);
> +
> +if (
> From: Roger Pau Monne
> Sent: Friday, July 1, 2022 9:17 PM
>
> @@ -225,6 +225,9 @@ static inline void pi_clear_sn(struct pi_desc *pi_desc)
>
> /*
> * Interruption-information format
> + *
> + * Note INTR_INFO_NMI_UNBLOCKED_BY_IRET is also used with Exit
> Qualification
> + * field under
> From: Roger Pau Monné
> Sent: Monday, July 4, 2022 6:07 PM
>
> On Mon, Jul 04, 2022 at 11:27:37AM +0200, Jan Beulich wrote:
> > On 01.07.2022 15:16, Roger Pau Monne wrote:
> > > --- a/xen/arch/x86/hvm/vmx/vmx.c
> > > +++ b/xen/arch/x86/hvm/vmx/vmx.c
> > > @@ -4065,6 +4065,11 @@ void
> From: Roger Pau Monne
> Sent: Friday, July 1, 2022 9:17 PM
>
> @@ -4065,6 +4065,11 @@ void vmx_vmexit_handler(struct cpu_user_regs
> *regs)
>
> if ( unlikely(exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) )
> return vmx_failed_vmentry(exit_reason, regs);
Add a blank line.
> +
> From: Jan Beulich
> Sent: Tuesday, July 5, 2022 8:45 PM
>
> Before actually enabling their use, provide a means to suppress it in
> case of problems. Note that using the option can also affect the sharing
> of page tables in the VT-d / EPT combination: If EPT would use large
> page mappings
> From: Jane Malalane
> Sent: Wednesday, June 29, 2022 9:56 PM
>
> Introduce a new per-domain creation x86 specific flag to
> select whether hardware assisted virtualization should be used for
> x{2}APIC.
>
> A per-domain option is added to xl in order to select the usage of
> x{2}APIC hardware
> From: Jane Malalane
> Sent: Wednesday, June 29, 2022 11:17 PM
>
> On 29/06/2022 15:26, Jan Beulich wrote:
> > On 29.06.2022 15:55, Jane Malalane wrote:
> >> Add XEN_SYSCTL_PHYSCAP_X86_ASSISTED_XAPIC and
> >> XEN_SYSCTL_PHYSCAP_X86_ASSISTED_X2APIC to report accelerated xAPIC
> and
> >> x2APIC,
> From: Roger Pau Monné
> Sent: Wednesday, June 29, 2022 5:11 PM
>
> On Wed, Jun 29, 2022 at 08:41:43AM +, Tian, Kevin wrote:
> > > From: Roger Pau Monne
> > > Sent: Monday, June 27, 2022 6:01 PM
> > >
> > > The current logic in
> From: Roger Pau Monné
> Sent: Tuesday, June 28, 2022 8:52 PM
>
> On Thu, Jun 09, 2022 at 12:17:23PM +0200, Jan Beulich wrote:
> > Before actually enabling their use, provide a means to suppress it in
> > case of problems. Note that using the option can also affect the sharing
> > of page
> From: Roger Pau Monne
> Sent: Monday, June 27, 2022 6:01 PM
>
> The current logic in epte_get_entry_emt() will split any page marked
> as special with order greater than zero, without checking whether the
> super page is all special.
>
> Fix this by only splitting the page only if it's not
> From: Roger Pau Monne
> Sent: Friday, May 20, 2022 9:38 PM
>
> Properly indent the handling of LBR enable in MSR_IA32_DEBUGCTLMSR
> vmx_msr_write_intercept().
>
> No functional change.
>
> Signed-off-by: Roger Pau Monné
Reviewed-by: Kevin Tian
> ---
> Feel free to squash onto the previous
+Chenyi/Xiaoyao who worked on the KVM support. Presumably
similar opens have been discussed in KVM hence they have the
right background to comment here.
> From: Roger Pau Monne
> Sent: Thursday, May 26, 2022 7:12 PM
>
> Under certain conditions guests can get the CPU stuck in an unbounded
>
> From: Roger Pau Monné
> Sent: Tuesday, June 7, 2022 6:06 PM
>
> On Tue, Jun 07, 2022 at 09:43:25AM +0200, Jan Beulich wrote:
> > On 03.06.2022 16:46, Roger Pau Monné wrote:
> > > On Fri, Jun 03, 2022 at 02:49:54PM +0200, Jan Beulich wrote:
> > >> On 26.05.2022 13:11, Roger Pau Monne wrote:
> >
> From: Jan Beulich
> Sent: Wednesday, May 18, 2022 6:26 PM
>
> On 10.05.2022 16:30, Roger Pau Monné wrote:
> > On Mon, Apr 25, 2022 at 10:42:50AM +0200, Jan Beulich wrote:
> >> When a page table ends up with no present entries left, it can be
> >> replaced by a non-present entry at the next
> From: Tamas K Lengyel
> Sent: Wednesday, May 18, 2022 11:02 PM
>
> On Thu, May 12, 2022 at 9:47 AM Tamas K Lengyel
> wrote:
> >
> > On Wed, May 4, 2022 at 9:12 AM Tamas K Lengyel
> wrote:
> > >
> > > On Wed, Apr 27, 2022 at 11:51 AM Tamas K Lengyel
> > > wrote:
> > > >
> > > > Add monitor
> From: Jan Beulich
> Sent: Thursday, May 19, 2022 8:20 PM
>
> On 22.04.2022 11:58, Jan Beulich wrote:
> > EPT is of no interest when !HVM. While I'm observing gcc11 to fully
> > eliminate the function, older gcc's DCE looks to not be as good. Aid the
> > compiler in eliminating the accesses of
> From: Jan Beulich
> Sent: Monday, April 25, 2022 4:45 PM
>
> This way intel_iommu_unmap_page() ends up quite a bit more similar to
> intel_iommu_map_page().
>
> No functional change intended.
>
> Signed-off-by: Jan Beulich
Reviewed-by: Kevin Tian
> ---
> v4: New.
>
> ---
> From: Jan Beulich
> Sent: Monday, April 25, 2022 4:45 PM
>
> With iommu_flush_iotlb_all() gone, iommu_flush_iotlb_pages() is merely a
> wrapper around the not otherwise called iommu_flush_iotlb(). Fold both
> functions.
>
> No functional change intended.
>
> Signed-off-by: Jan Beulich
> From: Jan Beulich
> Sent: Monday, April 25, 2022 4:43 PM
>
> When a page table ends up with no present entries left, it can be
> replaced by a non-present entry at the next higher level. The page table
> itself can then be scheduled for freeing.
>
> Note that while its output isn't used there
> From: Lengyel, Tamas
> Sent: Friday, March 25, 2022 9:33 PM
>
> During VM forking and resetting a failed vmentry has been observed due
> to the guest non-register state going out-of-sync with the guest register
> state. For example, a VM fork reset right after a STI instruction can trigger
>
> From: Andrew Cooper
> Sent: Wednesday, April 27, 2022 1:52 AM
>
> Hello,
>
> Edvin has found a machine with some very weird properties. It is an HP
> ProLiant BL460c Gen8 with:
>
> \-[:00]-+-00.0 Intel Corporation Xeon E5/Core i7 DMI2
> +-01.0-[11]--
>
> From: Tamas K Lengyel
> Sent: Tuesday, April 19, 2022 2:43 AM
>
> On Fri, Mar 25, 2022 at 9:34 AM Tamas K Lengyel
> wrote:
> >
> > During VM forking and resetting a failed vmentry has been observed due
> > to the guest non-register state going out-of-sync with the guest register
> > state.
> From: Jan Beulich
> Sent: Monday, April 11, 2022 5:42 PM
>
> At their use sites the numeric suffixes are at least odd to read, first
> and foremost for PCI_DEVFN2() where the suffix doesn't even match the
> number of arguments. Make use of count_args() such that a single flavor
> each suffices
> From: Jan Beulich
> Sent: Monday, April 11, 2022 5:40 PM
>
> There's no good reason to use these when we already have a pci_sbdf_t
> type object available. This extends to the use of PCI_BUS() in
> pci_ecam_map_bus() as well.
>
> No change to generated code (with gcc11 at least, and I have to
> From: Jan Beulich
> Sent: Monday, April 11, 2022 5:37 PM
>
> The field taking the value 7 (resulting in 18-bit DIDs when using the
> calculation in cap_ndoms(), when the DID fields are only 16 bits wide)
> is reserved. Instead of misbehaving in case we would encounter such an
> IOMMU, refuse
> From: Jan Beulich
> Sent: Monday, April 11, 2022 5:37 PM
>
> While 97af062b89d5 ("IOMMU/x86: maintain a per-device pseudo domain
> ID")
> took care of not making things worse, plugging pre-existing leaks wasn't
> the purpose of that change; they're not security relevant after all.
>
>
> From: Jan Beulich
> Sent: Monday, April 11, 2022 5:36 PM
>
> It's not only misplaced, but entirely unused.
>
> Signed-off-by: Jan Beulich
Reviewed-by: Kevin Tian
>
> --- a/xen/drivers/passthrough/vtd/iommu.h
> +++ b/xen/drivers/passthrough/vtd/iommu.h
> @@ -204,7 +204,6 @@ struct
> From: Jan Beulich
> Sent: Monday, April 11, 2022 5:36 PM
>
> Prior extension of these functions to enable per-device quarantine page
> tables already didn't add more locking there, but merely left in place
> what had been there before. But really locking is unnecessary here:
> We're running
> From: Jane Malalane
> Sent: Friday, April 1, 2022 6:47 PM
>
> Add XEN_SYSCTL_PHYSCAP_X86_ASSISTED_XAPIC and
> XEN_SYSCTL_PHYSCAP_X86_ASSISTED_X2APIC to report accelerated xAPIC
> and
> x2APIC, on x86 hardware. This is so that xAPIC and x2APIC virtualization
> can subsequently be enabled on a
> From: Jan Beulich
> Sent: Thursday, April 7, 2022 5:28 PM
>
> If get_iommu_domid() in domain_context_unmap_one() fails, we better
> wouldn't clear the context entry in the first place, as we're then unable
> to issue the corresponding flush. However, we have no need to look up the
> DID in the
> From: Jan Beulich
> Sent: Thursday, April 7, 2022 2:12 PM
>
> Despite the comment there infinite recursion was still possible, by
> flip-flopping between two domains. This is because prev_dom is derived
> from the DID found in the context entry, which was already updated by
> the time error
> From: Jan Beulich
> Sent: Thursday, April 7, 2022 3:50 PM
>
> On 07.04.2022 09:41, Roger Pau Monné wrote:
> > On Thu, Apr 07, 2022 at 08:11:06AM +0200, Jan Beulich wrote:
> >> First there's a printk() which actually wrongly uses pdev in the first
> >> place: We want to log the coordinates of
> From: Lengyel, Tamas
> Sent: Friday, March 25, 2022 9:33 PM
>
> During VM forking and resetting a failed vmentry has been observed due
> to the guest non-register state going out-of-sync with the guest register
> state. For example, a VM fork reset right after a STI instruction can trigger
>
> From: Jane Malalane
> Sent: Wednesday, March 16, 2022 5:13 PM
>
> Add XEN_SYSCTL_PHYSCAP_X86_ASSISTED_XAPIC and
> XEN_SYSCTL_PHYSCAP_X86_ASSISTED_X2APIC to report accelerated xAPIC
> and
> x2APIC, on x86 hardware. This is so that xAPIC and x2APIC virtualization
> can subsequently be enabled on
> From: Tamas K Lengyel
> Sent: Monday, March 14, 2022 8:14 PM
>
> On Mon, Mar 14, 2022 at 3:22 AM Tian, Kevin wrote:
> >
> > > From: Lengyel, Tamas
> > > Sent: Friday, March 11, 2022 2:45 AM
> > >
> > > During VM fork resetti
> From: Jan Beulich
> Sent: Monday, March 14, 2022 3:43 PM
>
> On 14.03.2022 07:35, Tian, Kevin wrote:
> >> From: Jan Beulich
> >> Sent: Monday, February 28, 2022 3:36 PM
> >>
> >> On 25.02.2022 18:11, Andrew Cooper wrote:
> >>> On 25/
> From: Jan Beulich
> Sent: Monday, March 14, 2022 3:33 PM
>
> On 14.03.2022 05:01, Tian, Kevin wrote:
> >> From: Jan Beulich
> >> Sent: Friday, February 18, 2022 4:31 PM
> >>
> >> On 18.02.2022 06:20, Tian, Kevin wrote:
> >>>> Fro
> From: Lengyel, Tamas
> Sent: Friday, March 11, 2022 2:45 AM
>
> During VM fork resetting a failed vmentry has been observed when the reset
> is performed immediately after a STI instruction executed. This is due to
> the guest interruptibility state in the VMCS being modified by STI but the
>
> From: Jane Malalane
> Sent: Monday, March 7, 2022 11:06 PM
>
> Add XEN_SYSCTL_PHYSCAP_ARCH_ASSISTED_xapic and
> XEN_SYSCTL_PHYSCAP_ARCH_ASSISTED_x2apic to report accelerated xapic
> and x2apic, on x86 hardware.
> No such features are currently implemented on AMD hardware.
>
> HW assisted
> From: Jan Beulich
> Sent: Monday, February 28, 2022 3:36 PM
>
> On 25.02.2022 18:11, Andrew Cooper wrote:
> > On 25/02/2022 13:19, Jan Beulich wrote:
> >> On 25.02.2022 13:28, Andrew Cooper wrote:
> >>> On 25/02/2022 08:44, Jan Beulich wrote:
> On 24.02.2022 20:48, Andrew Cooper wrote:
>
> From: Jan Beulich
> Sent: Tuesday, March 8, 2022 11:27 PM
>
> For an unknown reason I added back the operator while backporting,
> despite 4.16 having c06e3d810314 ("VT-d: per-domain IOMMU bitmap needs
> to have dynamic size"). I can only assume that I mistakenly took the
> 4.15 backport as
> From: Jan Beulich
> Sent: Monday, March 7, 2022 8:40 PM
>
> As of 3e56754b0887 ("xen/cet: Fix __initconst_cf_clobber") there's no
> need for a non-void return value anymore, as the hook functions are no
> longer themselves passed to __initcall(). For the same reason the
> iommu_enabled checks
> From: Roger Pau Monne
> Sent: Friday, February 25, 2022 12:37 AM
>
> Introduce a new field to mark devices as broken: having it set
> prevents the device from being assigned to guests. Use the field in
> order to mark ATS devices that have failed a flush as broken, thus
> preventing them to be
> From: Jan Beulich
> Sent: Friday, February 18, 2022 4:31 PM
>
> On 18.02.2022 06:20, Tian, Kevin wrote:
> >> From: Jan Beulich
> >> Sent: Tuesday, January 11, 2022 12:36 AM
> >>
> >> When a page table ends up with no present entries left
> From: Jan Beulich
> Sent: Friday, March 11, 2022 12:22 AM
>
> On 15.02.2022 14:27, Jan Beulich wrote:
> > On 15.02.2022 12:28, Roger Pau Monne wrote:
> >> After the removal of PVHv1 it's no longer supported to create a domain
> >> using hardware virtualization extensions and without a local
> From: Jan Beulich
> Sent: Friday, February 18, 2022 4:25 PM
>
> On 18.02.2022 06:01, Tian, Kevin wrote:
> >> From: Jan Beulich
> >> Sent: Tuesday, January 11, 2022 12:35 AM
> >>
> >> Page tables are used for two purposes after allocation: T
> From: Jan Beulich
> Sent: Thursday, January 27, 2022 10:50 PM
>
> The VT-d hook can indicate an error, which shouldn't be ignored. Convert
> the hook's return value to a proper error code, and let that bubble up.
>
> Signed-off-by: Jan Beulich
> ---
> I'm not convinced of the XSM related
> From: Jan Beulich
> Sent: Thursday, January 27, 2022 10:49 PM
>
> Let's use infrastructure we have available instead of an open-coded
> wbinvd() invocation.
>
> Signed-off-by: Jan Beulich
Reviewed-by: Kevin Tian
>
> --- a/xen/drivers/passthrough/vtd/extern.h
> +++
> From: Jan Beulich
> Sent: Thursday, January 27, 2022 10:48 PM
>
> The actual function should always have lived in core x86 code; move it
> there, replacing get_cache_line_size() by readily available (except very
> early during boot; see the code comment) data. Also rename the function.
>
>
> From: Andrew Cooper
> Sent: Friday, January 21, 2022 7:23 PM
>
> This is a trivial accessor for an MSR, so use hvm_get_reg() rather than a
> dedicated hook. In arch_get_info_guest(), rework the logic to read
> GS_SHADOW
> only once.
>
> get_hvm_registers() is called on current, meaning that
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:39 AM
>
> Signed-off-by: Jan Beulich
Reviewed-by: Kevin tian
> ---
> v3: New.
>
> --- a/xen/drivers/passthrough/amd/iommu_map.c
> +++ b/xen/drivers/passthrough/amd/iommu_map.c
> @@ -283,6 +283,8 @@ static int iommu_pde_from_dfn(struct
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:38 AM
>
> When a page table ends up with all contiguous entries (including all
> identical attributes), it can be replaced by a superpage entry at the
> next higher level. The page table itself can then be scheduled for
> freeing.
>
> The
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:36 AM
>
> When a page table ends up with no present entries left, it can be
> replaced by a non-present entry at the next higher level. The page table
> itself can then be scheduled for freeing.
>
> Note that while its output isn't used
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:35 AM
>
> Page tables are used for two purposes after allocation: They either
> start out all empty, or they get filled to replace a superpage.
> Subsequently, to replace all empty or fully contiguous page tables,
> contiguous sub-regions
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:34 AM
>
> Having a separate flush-all hook has always been puzzling me some. We
> will want to be able to force a full flush via accumulated flush flags
> from the map/unmap functions. Introduce a respective new flag and fold
> all flush
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:32 AM
>
> ... depending on feature availability (and absence of quirks).
>
> Also make the page table dumping function aware of superpages.
>
> Signed-off-by: Jan Beulich
Reviewed-by: Kevin Tian
> ---
> v3: Rename queue_free_pt()'s
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:23 AM
>
> I have to admit that I never understood why domain_pgd_maddr() wants to
> populate all page table levels for DFN 0. I can only assume that despite
> the comment there what is needed is population just down to the smallest
>
> From: Jan Beulich
> Sent: Tuesday, January 11, 2022 12:23 AM
>
> In order to be able to insert/remove super-pages we need to allow
> callers of the walking function to specify at which point to stop the
> walk.
>
> For intel_iommu_lookup_page() integrate the last level access into
> the main
> From: Beulich
> Sent: Wednesday, January 5, 2022 9:58 PM
>
> This has gone out of sync over time. Introduce a simplistic mechanism to
> hopefully keep things in sync going forward.
>
> Also limit the array index to just the "basic exit reason" part, which is
> what the pseudo-enumeration
> From: Jan Beulich
> Sent: Wednesday, December 1, 2021 12:11 AM
>
> ept_free_entry() gets called after a flush - if one is necessary in the
> first place - was already issued. That behavior is similar to NPT, which
> also doesn't have any further flush in p2m_free_entry(). (Furthermore,
> the
> From: Jan Beulich
> Sent: Thursday, December 9, 2021 11:52 PM
>
> While putting together patch 1, I've noticed two further aspects to
> clean up a little.
>
> 1: properly parenthesize a number of macros
> 2: use DMA_TLB_IVA_ADDR()
> 3: shorten vtd_flush_{context,iotlb}_reg()
>
Reviewed-by:
> From: Jan Beulich
> Sent: Friday, December 3, 2021 6:41 PM
>
> When an IOMMU implements the full 16 bits worth of DID in context
> entries, there's no point going through a memory base translation table.
> For IOMMUs not using Caching Mode we can simply use the domain IDs
> verbatim, while for
> From: Jan Beulich
> Sent: Thursday, December 2, 2021 4:48 PM
>
> On 01.12.2021 14:02, Andrew Cooper wrote:
> > On 01/12/2021 09:41, Jan Beulich wrote:
> >> --- a/xen/drivers/passthrough/vtd/iommu.c
> >> +++ b/xen/drivers/passthrough/vtd/iommu.c
> >> @@ -591,7 +591,8 @@ static int __must_check
> From: Jan Beulich
> Sent: Thursday, December 2, 2021 5:19 PM
>
> On 01.12.2021 15:39, Andrew Cooper wrote:
> > On 01/12/2021 09:40, Jan Beulich wrote:
> >> The actual function should always have lived in core x86 code; move it
> >> there, replacing get_cache_line_size() by readily available
> From: Jan Beulich
> Sent: Tuesday, November 23, 2021 9:40 PM
>
> As of commit 6773b1a7584a ("VT-d: Don't assume register-based
> invalidation is always supported") we don't (try to) use register based
> invalidation anymore when that's not supported by hardware. Hence
> there's also no point
> From: Jan Beulich
> Sent: Tuesday, November 23, 2021 9:40 PM
>
> All our present implementation requires is that the range fully fits
> in a single page. No need to exclude the case of the last register
> extending right to the end of that page.
>
> Signed-off-by: Jan Beulich
Reviewed-by:
> From: Jan Beulich
> Sent: Tuesday, November 23, 2021 9:40 PM
>
> Bit 0 of the capability register field has become reserved at or before
Bit 0 of 'SAGAW' in the capability register ...
> spec version 2.2. Treat it as such. Replace the effective open-coding of
> find_first_set_bit(). Adjust
> From: Jan Beulich
> Sent: Friday, November 12, 2021 5:50 PM
>
> When an IOMMU implements the full 16 bits worth of DID in context
> entries, there's no point going through a memory base translation table.
> For IOMMUs not using Caching Mode we can simply use the domain IDs
> verbatim, while
> From: Jan Beulich
> Sent: Friday, November 12, 2021 5:50 PM
>
> This is in preparation of adding another "translation" method. Take the
> combination of the extra validation both previously open-coded have been
> doing: Bounds check and bitmap check. But don't propagate the previous
>
> From: Jan Beulich
> Sent: Friday, November 12, 2021 5:49 PM
>
> - Correct struct field type.
> - Use unsigned int when that suffices.
> - Eliminate a (badly typed) local variable from
> context_set_domain_id().
> - Don't use -EFAULT inappropriately.
> - Move set_bit() such that it won't be
> From: Jan Beulich
> Sent: Friday, November 12, 2021 5:49 PM
>
> While domain_context_mapping() invokes domain_context_unmap() in a
> sub-
> case of handling DEV_TYPE_PCI when encountering an error, thus avoiding
> a leak, individual calls to domain_context_mapping_one() aren't
> similarly
1 - 100 of 571 matches
Mail list logo
