On 25.08.2020 12:37, George Dunlap wrote:
> As an explanation, there are a combination of things. You proposed A (remove
> the dependency), Ian proposed B (use move-if-changed), but we’re hoping to do
> C (have an external tree) before the next release. I haven’t had the time to
> look into
> On 25 Aug 2020, at 18:42, Julien Grall wrote:
>
> From: Julien Grall
>
> Commit 858c0be8c2fa "xen/arm: Enable CPU Erratum 1165522 for Neoverse"
> added a new erratum but forgot to update silicon-errata.txt.
>
> Update the file accordingly to keep track of errata workaround in Xen.
Oh i
On 26.08.20 08:20, Jan Beulich wrote:
> Hmm, to me __phys_to_virt() and __virt_to_phys_nodebug() give
> the impression that they're just linear transformations of the
> address, which would seem to suggest there's a pre-determined
> address range used for the direct map.
>From eyeballing the
> On 26 Aug 2020, at 08:46, Bertrand Marquis wrote:
>
>
>
>> On 25 Aug 2020, at 18:42, Julien Grall wrote:
>>
>> From: Julien Grall
>>
>> Commit 858c0be8c2fa "xen/arm: Enable CPU Erratum 1165522 for Neoverse"
>> added a new erratum but forgot to update silicon-errata.txt.
>>
>> Update
On 26.08.20 09:50, Simon Leiner wrote:
On 26.08.20 08:20, Jan Beulich wrote:
Hmm, to me __phys_to_virt() and __virt_to_phys_nodebug() give
the impression that they're just linear transformations of the
address, which would seem to suggest there's a pre-determined
address range used for the
Eduardo Habkost wrote:
> Generated using:
> $ ./scripts/codeconverter/converter.py -i --passes=2 \
> --pattern=TypeRegisterCall,TypeInitMacro $(git grep -l TypeInfo --
> '*.[ch]')
>
> One notable difference is that files declaring multiple types
> will now have multiple separate
[dropped people from CC]
Eduardo Habkost wrote:
> Some typedefs and macros are defined after the type check macros.
> This makes it difficult to automatically replace their
> definitions with OBJECT_DECLARE_TYPE.
>
> Patch generated using:
>
> $ ./scripts/codeconverter/converter.py -i \
>
Eduardo Habkost wrote:
> $ ./scripts/codeconverter/converter.py -i \
>--pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]')
>
> Reviewed-by: Daniel P. Berrangé
> Signed-off-by: Eduardo Habkost
> ---
> Changes v2 -> v3:
> * Removed hunks due to rebase conflicts:
> hw/arm/integratorcp.c
On 26.08.20 09:59, Jürgen Groß wrote:
> This seems to be an Arm specific function.
Is that a problem? The caller site is also ARM specific.
> virt_addr_valid() seems to be a good fit.
If you prefer that anyway, I will change it and resubmit that part of
the patch.
Simon
flight 152845 libvirt real [real]
http://logs.test-lab.xenproject.org/osstest/logs/152845/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-amd64-libvirt 6 libvirt-buildfail REGR. vs. 151777
build-i386-libvirt
flight 152826 xen-unstable real [real]
http://logs.test-lab.xenproject.org/osstest/logs/152826/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-amd64-qemuu-nested-amd 14 xen-boot/l1 fail REGR. vs. 152779
Tests which did
On 26.08.2020 01:48, Stefano Stabellini wrote:
> On Tue, 25 Aug 2020, Jan Beulich wrote:
>> On 25.08.2020 11:31, Simon Leiner wrote:
>>> --- a/include/xen/arm/page.h
>>> +++ b/include/xen/arm/page.h
>>> @@ -76,7 +76,11 @@ static inline unsigned long bfn_to_pfn(unsigned long bfn)
>>> #define
The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg() function
returns the number of the created entries in the DMA address space.
However the subsequent calls to the dma_sync_sg_for_{device,cpu}() and
dma_unmap_sg must be called with the original number of the entries
passed to the
The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg() function
returns the number of the created entries in the DMA address space.
However the subsequent calls to the dma_sync_sg_for_{device,cpu}() and
dma_unmap_sg must be called with the original number of the entries
passed to the
On 26/08/2020 08:46, Bertrand Marquis wrote:
On 25 Aug 2020, at 18:42, Julien Grall wrote:
From: Julien Grall
Commit 858c0be8c2fa "xen/arm: Enable CPU Erratum 1165522 for Neoverse"
added a new erratum but forgot to update silicon-errata.txt.
Update the file accordingly to keep track
flight 152854 xen-unstable-coverity real [real]
http://logs.test-lab.xenproject.org/osstest/logs/152854/
Perfect :-)
All tests in this flight passed as required
version targeted for testing:
xen 7a8d8bde9820387c3e168182b99fd9761c223fff
baseline version:
xen
On Wed, Aug 26 2020 at 16:40, Boqun Feng wrote:
> I hit a compiler error while I was trying to compile this patchset:
>
> arch/x86/kernel/devicetree.c: In function ‘dt_irqdomain_alloc’:
> arch/x86/kernel/devicetree.c:232:6: error: ‘struct irq_alloc_info’ has no
> member named ‘ioapic_id’; did you
flight 152836 qemu-mainline real [real]
http://logs.test-lab.xenproject.org/osstest/logs/152836/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-qemuu-rhel6hvm-amd 10 redhat-install fail REGR. vs. 152631
> On 26 Aug 2020, at 10:37, Julien Grall wrote:
>
>
>
> On 26/08/2020 08:46, Bertrand Marquis wrote:
>>> On 25 Aug 2020, at 18:42, Julien Grall wrote:
>>>
>>> From: Julien Grall
>>>
>>> Commit 858c0be8c2fa "xen/arm: Enable CPU Erratum 1165522 for Neoverse"
>>> added a new erratum but forgot
On 26.08.20 10:14, Simon Leiner wrote:
On 26.08.20 09:59, Jürgen Groß wrote:
This seems to be an Arm specific function.
Is that a problem? The caller site is also ARM specific.
The caller site is ARM specific, but __is_lm_address() is defined for
arm64 only.
virt_addr_valid() seems to
On 26.08.20 10:27, Jürgen Groß wrote:
> On 26.08.20 10:14, Simon Leiner wrote:
>> On 26.08.20 09:59, Jürgen Groß wrote:
>>> This seems to be an Arm specific function.
>>
>> Is that a problem? The caller site is also ARM specific.
>
> The caller site is ARM specific, but __is_lm_address() is
Hi Thomas,
I hit a compiler error while I was trying to compile this patchset:
arch/x86/kernel/devicetree.c: In function ‘dt_irqdomain_alloc’:
arch/x86/kernel/devicetree.c:232:6: error: ‘struct irq_alloc_info’ has no
member named ‘ioapic_id’; did you mean ‘ioapic’?
232 | tmp.ioapic_id =
Now that the domain can be retrieved through device::msi_domain the domain
search for PCI_MSI[X] is not longer required. Remove it.
Signed-off-by: Thomas Gleixner
---
V2: New patch
---
drivers/iommu/intel/irq_remapping.c |3 ---
1 file changed, 3 deletions(-)
---
From: Thomas Gleixner
Move the IOAPIC specific fields into their own struct and reuse the common
devid. Get rid of the #ifdeffery as it does not matter at all whether the
alloc info is a couple of bytes longer or not.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/hw_irq.h |
From: Thomas Gleixner
The arch_.*_msi_irq[s] fallbacks are compiled in whether an architecture
requires them or not. Architectures which are fully utilizing hierarchical
irq domains should never call into that code.
It's not only architectures which depend on that by implementing one or
more of
From: Thomas Gleixner
Rename it to x86_msi_prepare() and handle the allocation type setup
depending on the device type.
Add a new arch_msi_prepare define which will be utilized by the upcoming
device MSI support. Define it to NULL if not provided by an architecture in
the generic MSI header.
Generic IMS irq chips and irq domain implementations for IMS based devices
in both variants:
- Message store in an array in device memory
- Message store in system RAM (part of queue memory)
Allocation and freeing of interrupts happens via the generic
msi_domain_alloc/free_irqs()
From: Thomas Gleixner
No point to call it from both 32bit and 64bit implementations of
default_setup_apic_routing(). Move it to the caller.
Signed-off-by: Thomas Gleixner
---
arch/x86/kernel/apic/apic.c |3 +++
arch/x86/kernel/apic/probe_32.c |3 ---
From: Thomas Gleixner
Nothing except XEN uses the setup/teardown ops. Hide them there.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/x86_init.h |2 --
arch/x86/pci/xen.c | 21 ++---
2 files changed, 14 insertions(+), 9 deletions(-)
---
From: Thomas Gleixner
For devices which don't have a standard storage for MSI messages like the
upcoming IMS (Interrupt Message Storm) it's required to allocate storage
space before allocating interrupts and after freeing them.
This could be achieved with the existing callbacks, but that would
From: Thomas Gleixner
The only user is in the same file and the name is too generic because this
function is only ever used for HVM domains.
Signed-off-by: Thomas Gleixner
Reviewed-by: Juergen Gross
---
arch/x86/pci/xen.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
---
Now that the domain can be retrieved through device::msi_domain the domain
search for PCI_MSI[X] is not longer required. Remove it.
Signed-off-by: Thomas Gleixner
---
V2: New patch
---
drivers/iommu/amd/iommu.c |3 ---
1 file changed, 3 deletions(-)
--- a/drivers/iommu/amd/iommu.c
+++
From: Thomas Gleixner
Move the UV specific fields into their own struct for readability sake. Get
rid of the #ifdeffery as it does not matter at all whether the alloc info
is a couple of bytes longer or not.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/hw_irq.h | 21
From: Thomas Gleixner
Devices on the VMD bus use their own MSI irq domain, but it is not
distinguishable from regular PCI/MSI irq domains. This is required
to exclude VMD devices from getting the irq domain pointer set by
interrupt remapping.
Override the default bus token.
Signed-off-by:
From: Thomas Gleixner
As a first step to make X86 utilize the direct MSI irq domain operations
store the irq domain pointer in the device struct when a device is probed.
This is done from dmar_pci_bus_add_dev() because it has to work even when
DMA remapping is disabled. It only overrides the
MSI interrupts have some common flags which should be set not only for
PCI/MSI interrupts.
Move the PCI/MSI flag setting into a common function so it can be reused.
Signed-off-by: Thomas Gleixner
---
V2: New patch
---
drivers/pci/msi.c |7 +--
include/linux/msi.h |1 +
From: Thomas Gleixner
To allow utilizing the irq domain pointer in struct device it is necessary
to make XEN/MSI irq domain compatible.
While the right solution would be to truly convert XEN to irq domains, this
is an exercise which is not possible for mere mortals with limited XENology.
From: Thomas Gleixner
Get rid of all the gunk and remove the 'select PCI_MSI_ARCH_FALLBACK' from
the x86 Kconfig so the weak functions in the PCI core are replaced by stubs
which emit a warning, which ensures that any fail to set the irq domain
pointer results in a warning when the device is
From: Thomas Gleixner
Adding a function call before the first #ifdef in arch_pci_init() triggers
a 'mixed declarations and code' warning if PCI_DIRECT is enabled.
Use stub functions and move the #ifdeffery to the header file where it is
not in the way.
Signed-off-by: Thomas Gleixner
---
From: Thomas Gleixner
None of the magic HPET fields are required in any way.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/hw_irq.h |7 ---
arch/x86/kernel/apic/msi.c | 14 +++---
drivers/iommu/amd/iommu.c |2 +-
From: Thomas Gleixner
Convert the interrupt remap drivers to retrieve the pci device from the msi
descriptor and use info::hwirq.
This is the first step to prepare x86 for using the generic MSI domain ops.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/hw_irq.h |8
From: Thomas Gleixner
Add device specific MSI domain infrastructure for devices which have their
own resource management and interrupt chip. These devices are not related
to PCI and contrary to platform MSI they do not share a common resource and
interrupt chip. They provide their own domain
From: Thomas Gleixner
For the upcoming device MSI support it's required to have a default
irq_chip::ack implementation (irq_chip_ack_parent) so the drivers do not
need to care.
Signed-off-by: Thomas Gleixner
---
drivers/base/platform-msi.c |2 ++
1 file changed, 2 insertions(+)
---
From: Thomas Gleixner
No point in initializing the default PCI/MSI interrupt domain early and no
point to create it when XEN PV/HVM/DOM0 are active.
Move the initialization to pci_arch_init() and convert it to init ops so
that XEN can override it as XEN has it's own PCI/MSI management. The XEN
From: Thomas Gleixner
As the next step to make X86 utilize the direct MSI irq domain operations
store the irq domain pointer in the device struct when a device is probed.
It only overrides the irqdomain of devices which are handled by a regular
PCI/MSI irq domain which protects PCI devices
From: Thomas Gleixner
PCI devices behind a VMD bus are not subject to interrupt remapping, but
the irq domain for VMD MSI cannot be distinguished from a regular PCI/MSI
irq domain.
Add a new domain bus token and allow it in the bus token check in
msi_check_reservation_mode() to keep the
VMD has it's own PCI/MSI interrupt domain which is not in any way depending
on the x86 vector domain. PCI devices behind VMD share the VMD MSIX vector
entries via a VMD specific message translation to the actual VMD MSIX
vector. The VMD device interrupt handler for the VMD MSIX vectors invokes
all
Composing the MSI message at the MSI chip level is wrong because the
underlying parent domain is the one which knows how the message should be
composed for the direct vector delivery or the interrupt remapping table
entry.
The interrupt remapping aware PCI/MSI chip does that already. Make the
Setting the irq_set_vcpu_affinity() callback to
irq_chip_set_vcpu_affinity_parent() is a pointless exercise because the
function which utilizes it searchs the domain hierarchy to find a parent
domain which has such a callback.
Remove the useless indirection.
Signed-off-by: Thomas Gleixner
---
From: Thomas Gleixner
Retrieve the PCI device from the msi descriptor instead of doing so at the
call sites.
Signed-off-by: Thomas Gleixner
Acked-by: Bjorn Helgaas
---
V2: Address Bjorns comments (subject prefix, pdev/dev)
---
arch/x86/kernel/apic/msi.c |2 +-
drivers/pci/msi.c
From: Thomas Gleixner
pci_msi_get_hwirq() and pci_msi_set_desc are not longer special. Enable the
generic MSI domain ops in the core and PCI MSI code unconditionally and get
rid of the x86 specific implementations in the X86 MSI code and in the
hyperv PCI driver.
Signed-off-by: Thomas Gleixner
The documentation of irq_chip_compose_msi_msg() claims that with
hierarchical irq domains the first chip in the hierarchy which has an
irq_compose_msi_msg() callback is chosen. But the code just keeps
iterating after it finds a chip with a compose callback.
The x86 HPET MSI implementation relies
From: Thomas Gleixner
Now that the iommu implementations handle the X86_*_GET_PARENT_DOMAIN
types, consolidate the two getter functions.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/irq_remapping.h |8
arch/x86/kernel/apic/io_apic.c |2 +-
From: Thomas Gleixner
Dereferencing irq_data before checking it for NULL is suboptimal.
Signed-off-by: Thomas Gleixner
---
drivers/iommu/amd/iommu.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -3717,8
From: Thomas Gleixner
None of the DMAR specific fields are required.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/hw_irq.h |6 --
arch/x86/kernel/apic/msi.c| 10 +-
2 files changed, 5 insertions(+), 11 deletions(-)
--- a/arch/x86/include/asm/hw_irq.h
+++
This is the second version of providing a base to support device MSI (non
PCI based) and on top of that support for IMS (Interrupt Message Storm)
based devices in a halfways architecture independent way.
The first version can be found here:
From: Thomas Gleixner
No functional change.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/hw_irq.h |4 ++--
arch/x86/kernel/apic/msi.c |6 +++---
drivers/iommu/amd/iommu.c | 24
drivers/iommu/intel/irq_remapping.c | 18
From: Thomas Gleixner
Provide a helper function to check whether a PCI device is handled by a
non-standard PCI/MSI domain. This will be used to exclude such devices
which hang of a special bus, e.g. VMD, to be excluded from the irq domain
override in irq remapping.
Signed-off-by: Thomas
From: Thomas Gleixner
struct irq_alloc_info is a horrible zoo of unnamed structs in a union. Many
of the struct fields can be generic and don't have to be type specific like
hpet_id, ioapic_id...
Provide a generic set of members to prepare for the consolidation. The goal
is to make
From: Thomas Gleixner
To support MSI irq domains which do not fit at all into the regular MSI
irqdomain scheme, like the XEN MSI interrupt management for PV/HVM/DOM0,
it's necessary to allow to override the alloc/free implementation.
This is a preperatory step to switch X86 away from
From: Thomas Gleixner
X86 cannot store the irq domain pointer in struct device without breaking
XEN because the irq domain pointer takes precedence over arch_*_msi_irqs()
fallbacks.
XENs MSI teardown relies on default_teardown_msi_irqs() which invokes
arch_teardown_msi_irq().
On 26.08.2020 12:33, George Dunlap wrote:
>
>
>> On Aug 26, 2020, at 8:41 AM, Jan Beulich wrote:
>>
>> On 25.08.2020 12:37, George Dunlap wrote:
>>> As an explanation, there are a combination of things. You proposed A
>>> (remove the dependency), Ian proposed B (use move-if-changed), but we’re
From: Thomas Gleixner
Some past platform removal forgot to get rid of this unused ballast.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/mpspec.h | 10 --
arch/x86/include/asm/x86_init.h | 10 --
arch/x86/kernel/mpparse.c | 26
From: Thomas Gleixner
The irq domain request mode is now indicated in irq_alloc_info::type.
Consolidate the two getter functions into one.
Signed-off-by: Thomas Gleixner
---
drivers/iommu/intel/irq_remapping.c | 67
1 file changed, 24 insertions(+), 43
From: Thomas Gleixner
irq_remapping_ir_irq_domain() is used to retrieve the remapping parent
domain for an allocation type. irq_remapping_irq_domain() is for retrieving
the actual device domain for allocating interrupts for a device.
The two functions are similar and can be unified by using
From: Thomas Gleixner
The irq domain request mode is now indicated in irq_alloc_info::type.
Consolidate the two getter functions into one.
Signed-off-by: Thomas Gleixner
---
drivers/iommu/amd/iommu.c | 65 ++
1 file changed, 21 insertions(+), 44
From: Thomas Gleixner
Now that interrupt remapping sets the irqdomain pointer when a PCI device
is added it's possible to store the default irq domain in the device struct
in pcibios_add_device().
If the bus to which a device is connected has an irq domain associated then
this domain is used
Until now interrupt chips which support setting affinity are nit locking
the associated bus lock for two reasons:
- All chips which support affinity setting do not use buslock because they just
can operated directly on the hardware.
- All chips which use buslock do not support affinity
From: Thomas Gleixner
For the upcoming device MSI support a new allocation type is
required.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/hw_irq.h |1 +
1 file changed, 1 insertion(+)
--- a/arch/x86/include/asm/hw_irq.h
+++ b/arch/x86/include/asm/hw_irq.h
@@ -40,6 +40,7 @@
From: Thomas Gleixner
X86 cannot store the irq domain pointer in struct device without breaking
XEN because the irq domain pointer takes precedence over arch_*_msi_irqs()
fallbacks.
To achieve this XEN MSI interrupt management needs to be wrapped into an
irq domain.
Move the x86_msi ops setup
On 24.08.2020 18:58, Andrew Cooper wrote:
> ... including serialisation/deserialisation logic and unit tests.
>
> There is no current way to configure this MSR correctly for guests.
> The toolstack side this logic needs building, which is far easier to
> do with it in place.
>
> Signed-off-by:
On 18.08.2020 12:30, Paul Durrant wrote:
> v7:
> - Add an option to domain_load_end() to ignore unconsumed data, which will
>be needed by a subsequent patch
May I suggest to name the parameter "ignore_tail" instead of
"ignore_data", as typically you don't mean to ignore all of
it?
Jan
I am changing my email address. (My affiliation to Citrix remains
unchanged.) See
https://xenbits.xen.org/people/iwj/2020/email-transition.txt
for a signed confirmation with full details.
Signed-off-by: Ian Jackson
Signed-off-by: Ian Jackson
---
MAINTAINERS | 8
1 file changed, 4
flight 152842 linux-linus real [real]
http://logs.test-lab.xenproject.org/osstest/logs/152842/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-xl-xsm7 xen-boot fail REGR. vs. 152332
LLVM 11 complains with:
:1:1: error: changed section flags for .init.rodata, expected:
0x2
.pushsection .init.rodata
^
:30:9: note: while in macro instantiation
entrypoint 0
^
entry.S:979:9: note: while in macro instantiation
.rept 256
^
And:
entry.S:1015:9:
On Wed, Aug 26 2020 at 09:50, Megha Dey wrote:
>> @@ -329,15 +329,15 @@ static struct irq_chip dmar_msi_controll
>> static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
>>msi_alloc_info_t *arg)
>> {
>> -return arg->dmar_id;
>> +
On Wed, Aug 26 2020 at 13:17, Thomas Gleixner wrote:
> + * If CONFIG_PCI_MSI_ARCH_FALLBACKS is not selected they are replaced by
> + * stubs with warnings.
> */
> +#ifdef CONFIG_PCI_MSI_DISABLE_ARCH_FALLBACKS
Groan, I obviously failed to pull that back from the test box where I
fixed it. That
On 26.08.2020 15:51, Roger Pau Monne wrote:
> LLVM 11 complains with:
>
> :1:1: error: changed section flags for .init.rodata, expected:
> 0x2
> .pushsection .init.rodata
> ^
> :30:9: note: while in macro instantiation
> entrypoint 0
> ^
> entry.S:979:9: note: while in macro
On Tue, Aug 25, 2020 at 03:21:08PM -0400, Eduardo Habkost wrote:
> This will remove instance_size/class_size fields from TypeInfo
> variables when the value is exactly the same as the one in the
> parent class.
>
> Generated by:
>
> $ ./scripts/codeconverter/converter.py -i \
>
Hi Simon,
On 25/08/2020 10:31, Simon Leiner wrote:
As virt_to_gfn uses virt_to_phys, it will return invalid addresses when
used with vmalloc'd addresses. This patch introduces a warning, when
virt_to_gfn is used in this way.
Signed-off-by: Simon Leiner
---
include/xen/arm/page.h | 6 +-
On Wed, 26 Aug 2020, Bertrand Marquis wrote:
> > On 26/08/2020 08:46, Bertrand Marquis wrote:
> >>> On 25 Aug 2020, at 18:42, Julien Grall wrote:
> >>>
> >>> From: Julien Grall
> >>>
> >>> Commit 858c0be8c2fa "xen/arm: Enable CPU Erratum 1165522 for Neoverse"
> >>> added a new erratum but forgot
> On Aug 26, 2020, at 8:41 AM, Jan Beulich wrote:
>
> On 25.08.2020 12:37, George Dunlap wrote:
>> As an explanation, there are a combination of things. You proposed A (remove
>> the dependency), Ian proposed B (use move-if-changed), but we’re hoping to
>> do C (have an external tree) before
Hi Thomas,
On 8/26/2020 4:16 AM, Thomas Gleixner wrote:
From: Thomas Gleixner
None of the DMAR specific fields are required.
Signed-off-by: Thomas Gleixner
---
arch/x86/include/asm/hw_irq.h |6 --
arch/x86/kernel/apic/msi.c| 10 +-
2 files changed, 5
On Wed, 26 Aug 2020 12:16:45 +0100,
Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Retrieve the PCI device from the msi descriptor instead of doing so at the
> call sites.
>
> Signed-off-by: Thomas Gleixner
> Acked-by: Bjorn Helgaas
Acked-by: Marc Zyngier
M.
--
Without
On Wed, 26 Aug 2020 20:47:38 +0100,
Thomas Gleixner wrote:
>
> On Wed, Aug 26 2020 at 20:06, Marc Zyngier wrote:
> > On Wed, 26 Aug 2020 12:16:57 +0100,
> > Thomas Gleixner wrote:
> >> /**
> >> - * msi_domain_free_irqs - Free interrupts from a MSI interrupt @domain
> >> associated tp @dev
>
flight 152853 linux-5.4 real [real]
http://logs.test-lab.xenproject.org/osstest/logs/152853/
Failures :-/ but no regressions.
Tests which did not succeed, but are not blocking:
test-amd64-i386-xl-pvshim12 guest-start fail never pass
test-amd64-i386-libvirt-xsm 13
On Wed, Aug 26 2020 at 22:14, Marc Zyngier wrote:
> On Wed, 26 Aug 2020 12:17:02 +0100,
> Thomas Gleixner wrote:
>> @@ -103,6 +105,7 @@ config PCIE_XILINX_CPM
>> bool "Xilinx Versal CPM host bridge support"
>> depends on ARCH_ZYNQMP || COMPILE_TEST
>> select PCI_HOST_COMMON
>> +
On Wed, 26 Aug 2020 12:16:51 +0100,
Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> PCI devices behind a VMD bus are not subject to interrupt remapping, but
> the irq domain for VMD MSI cannot be distinguished from a regular PCI/MSI
> irq domain.
>
> Add a new domain bus token and allow
On Wed, Aug 26 2020 at 21:21, Marc Zyngier wrote:
> On Wed, 26 Aug 2020 12:16:47 +0100,
> Thomas Gleixner wrote:
>> -void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
>> -{
>> -arg->desc = desc;
>> -arg->hwirq = pci_msi_domain_calc_hwirq(desc);
>> -}
>>
On Wed, Aug 26 2020 at 20:32, Thomas Gleixner wrote:
> On Wed, Aug 26 2020 at 09:50, Megha Dey wrote:
>>> @@ -329,15 +329,15 @@ static struct irq_chip dmar_msi_controll
>>> static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
>>>
On Wed, 26 Aug 2020 12:17:09 +0100,
Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> For the upcoming device MSI support it's required to have a default
> irq_chip::ack implementation (irq_chip_ack_parent) so the drivers do not
> need to care.
>
> Signed-off-by: Thomas Gleixner
>
> ---
flight 152856 qemu-mainline real [real]
http://logs.test-lab.xenproject.org/osstest/logs/152856/
Regressions :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
test-amd64-i386-qemuu-rhel6hvm-amd 10 redhat-install fail REGR. vs. 152631
On Wed, Aug 26 2020 at 20:06, Marc Zyngier wrote:
> On Wed, 26 Aug 2020 12:16:57 +0100,
> Thomas Gleixner wrote:
>> /**
>> - * msi_domain_free_irqs - Free interrupts from a MSI interrupt @domain
>> associated tp @dev
>> - * @domain: The domain to managing the interrupts
>> + *
On Wed, 26 Aug 2020 12:16:47 +0100,
Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> pci_msi_get_hwirq() and pci_msi_set_desc are not longer special. Enable the
> generic MSI domain ops in the core and PCI MSI code unconditionally and get
> rid of the x86 specific implementations in the
On Wed, 26 Aug 2020 12:16:52 +0100,
Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> Devices on the VMD bus use their own MSI irq domain, but it is not
> distinguishable from regular PCI/MSI irq domains. This is required
> to exclude VMD devices from getting the irq domain pointer set by
>
On Wed, Aug 26 2020 at 20:50, Marc Zyngier wrote:
> On Wed, 26 Aug 2020 12:16:32 +0100,
> Thomas Gleixner wrote:
>> ---
>> V2: New patch. Note, that this might break other stuff which relies on the
>> current behaviour, but the hierarchy composition of DT based chips is
>> really hard to
On Wed, 26 Aug 2020 12:16:57 +0100,
Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> To support MSI irq domains which do not fit at all into the regular MSI
> irqdomain scheme, like the XEN MSI interrupt management for PV/HVM/DOM0,
> it's necessary to allow to override the alloc/free
On Wed, 26 Aug 2020 12:16:32 +0100,
Thomas Gleixner wrote:
>
> The documentation of irq_chip_compose_msi_msg() claims that with
> hierarchical irq domains the first chip in the hierarchy which has an
> irq_compose_msi_msg() callback is chosen. But the code just keeps
> iterating after it finds a
On Wed, 26 Aug 2020 12:17:02 +0100,
Thomas Gleixner wrote:
>
> From: Thomas Gleixner
>
> The arch_.*_msi_irq[s] fallbacks are compiled in whether an architecture
> requires them or not. Architectures which are fully utilizing hierarchical
> irq domains should never call into that code.
>
>
On Wed, 26 Aug 2020 22:19:56 +0100,
Thomas Gleixner wrote:
>
> On Wed, Aug 26 2020 at 20:50, Marc Zyngier wrote:
> > On Wed, 26 Aug 2020 12:16:32 +0100,
> > Thomas Gleixner wrote:
> >> ---
> >> V2: New patch. Note, that this might break other stuff which relies on the
> >> current
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