>>> On 30.01.19 at 10:52, wrote:
> On 2019/1/26 1:48, Jan Beulich wrote:
> On 20.12.18 at 14:14, wrote:
>>> The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and
>>> counter MSRs, hardware configuration MSR, MMIO configuration base address
>>> MSR, MPERF/APERF MSRs) as AMD
On 2019/1/26 1:48, Jan Beulich wrote:
On 20.12.18 at 14:14, wrote:
>> The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and
>> counter MSRs, hardware configuration MSR, MMIO configuration base address
>> MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support
>>> On 20.12.18 at 14:14, wrote:
> The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and
> counter MSRs, hardware configuration MSR, MMIO configuration base address
> MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support to the
> PV emulation infrastructure by
The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and
counter MSRs, hardware configuration MSR, MMIO configuration base address
MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support to the
PV emulation infrastructure by using the code path of AMD.
As hygon.c needs
