[Xen-devel] [PATCH] build: add --with-rundir option to configure

There have been reports that Fedora 25 uses /run instead of /var/run. Add a --with-rundir option ito configure to be able to specify that directory. Default is still /var/run. A re-run of autogen.sh is required. Signed-off-by: Juergen Gross --- Backport candidate (at least

[Xen-devel] [xen-unstable-smoke test] 105836: tolerable trouble: broken/fail/pass - PUSHED

flight 105836 xen-unstable-smoke real [real] http://logs.test-lab.xenproject.org/osstest/logs/105836/ Failures :-/ but no regressions. Tests which did not succeed, but are not blocking: test-arm64-arm64-xl-xsm 1 build-check(1) blocked n/a build-arm64 5

[Xen-devel] qemu crashes during VCPU hotplug

Upstream qemu appears to be crashing during VCPU hotplug. I think this is something relatively new since I have been doing this a few week ago. I reproduced on two different setups. Haven't had a chance to look any further but e3cadac073 looks suspicious. The crash happens in

Re: [Xen-devel] Install of Xen 4.8 on Fedora 25 makes the box unbootable.. which is due to /var/run/xen being created, instead of /run/xen

On 15/02/17 22:10, Boris Ostrovsky wrote: > On 02/15/2017 03:51 PM, Konrad Rzeszutek Wilk wrote: >> Hey, >> >> Credit goes to Boris (CC-ed) for figuring out how to fix this. >> >> I was doing: >> >> ./configure --prefix=/usr --enable-systemd >> make -j8 >> cd dist;./install.sh;) >> reboot >> >>

[Xen-devel] [xen-unstable test] 105821: tolerable FAIL - PUSHED

flight 105821 xen-unstable real [real] http://logs.test-lab.xenproject.org/osstest/logs/105821/ Failures :-/ but no regressions. Regressions which are regarded as allowable (not blocking): test-armhf-armhf-libvirt 13 saverestore-support-checkfail like 105804

Re: [Xen-devel] Install of Xen 4.8 on Fedora 25 makes the box unbootable.. which is due to /var/run/xen being created, instead of /run/xen

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Am Wed, 15 Feb 2017 15:51:12 -0500 schrieb Konrad Rzeszutek Wilk : > mkdir /run/xen > mkdir /run/xenstored This must be done by the startup scripts because the "run" directories, where ever they are, are volatile. I think

Re: [Xen-devel] Install of Xen 4.8 on Fedora 25 makes the box unbootable.. which is due to /var/run/xen being created, instead of /run/xen

On 16/02/17 08:52, Olaf Hering wrote: > Am Wed, 15 Feb 2017 15:51:12 -0500 > schrieb Konrad Rzeszutek Wilk : >> mkdir /run/xen >> mkdir /run/xenstored > > This must be done by the startup scripts because the "run" directories, > where ever they are, are volatile. > > I

[Xen-devel] (resend) qemu crashes during VCPU hotplug

(Now with correct address for Stefano) Upstream qemu appears to be crashing during VCPU hotplug. I think this is something relatively new since I have been doing this a few week ago. I reproduced this on two different setups. Haven't had a chance to look any further but e3cadac073 looks

[Xen-devel] [xtf test] 105823: all pass - PUSHED

flight 105823 xtf real [real] http://logs.test-lab.xenproject.org/osstest/logs/105823/ Perfect :-) All tests in this flight passed as required version targeted for testing: xtf 01b0192030c01dc8af02dca6b92d720cf3908b80 baseline version: xtf

[Xen-devel] [PATCH RFC V2 4/7] COLO-Proxy: Setup userspace colo-proxy on secondary side

In this patch we add a function to close COLO kernel Proxy on secondary side. Signed-off-by: Zhang Chen --- tools/libxl/libxl_colo_restore.c | 8 ++-- tools/libxl/libxl_create.c | 8 ++-- tools/libxl/libxl_types.idl | 1 +

[Xen-devel] [PATCH RFC V2 7/7] COLO-Proxy: Use socket to get checkpoint event.

We use kernel colo proxy's way to get the checkpoint event from qemu colo-compare. Qemu colo-compare need add a API to support this(I will add this in qemu). Signed-off-by: Zhang Chen --- tools/libxl/libxl_colo.h | 2 + tools/libxl/libxl_colo_proxy.c |

[Xen-devel] [PATCH RFC V2 1/7] COLO-Proxy: Add remus command to open userspace proxy

Add remus '-p' to enable userspace colo proxy(in qemu). Signed-off-by: Zhang Chen --- docs/man/xl.pod.1.in | 5 + tools/libxl/libxl.h | 6 ++ tools/libxl/libxl_colo.h | 5 + tools/libxl/libxl_colo_save.c | 2 ++

[Xen-devel] [PATCH RFC V2 3/7] tools/libxl: refactor do_domain_create()

We use params->colo_proxy_script to make do_domain_create() doesn't take "colo_proxy_script" anymore. Signed-off-by: Zhang Chen --- tools/libxl/libxl_create.c | 17 ++--- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git

[Xen-devel] [PATCH RFC V2 5/7] COLO-Proxy: Add primary userspace colo proxy start args

Qemu need this args to start userspace colo-proxy. Signed-off-by: Zhang Chen --- tools/libxl/libxl_dm.c | 98 + tools/libxl/libxl_nic.c | 78 tools/libxl/libxl_types.idl | 31

[Xen-devel] [PATCH RFC V2 2/7] COLO-Proxy: Setup userspace colo-proxy on primary side

In this patch we close kernel COLO-Proxy on primary side. Signed-off-by: Zhang Chen --- tools/libxl/libxl_colo_proxy.c | 27 +++ tools/libxl/libxl_colo_save.c | 9 +++-- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git

[Xen-devel] [PATCH RFC V2 6/7] COLO-Proxy: Add secondary userspace colo-proxy start args

Qemu need this args to start userspace colo-proxy. Signed-off-by: Zhang Chen --- tools/libxl/libxl_dm.c | 34 ++ tools/libxl/libxl_nic.c | 27 +++ tools/libxl/libxl_types.idl | 15 ++-

[Xen-devel] [PATCH RFC V2 0/7] COLO-Proxy: Make Xen COLO use userspace colo-proxy

Because of some reason, We no longer support COLO kernel proxy. So we send this patch set to make Xen use userspace colo-proxy in qemu. Below is a COLO userspace proxy ascii figure: Primary qemu Secondary qemu

[Xen-devel] [ovmf test] 105808: all pass - PUSHED

flight 105808 ovmf real [real] http://logs.test-lab.xenproject.org/osstest/logs/105808/ Perfect :-) All tests in this flight passed as required version targeted for testing: ovmf 5e9e151c2061cc10e5aa9f41c6f1d7d1b865954e baseline version: ovmf

Re: [Xen-devel] Unable to boot Xen 4.8 with iommu=0

>>> On 15.02.17 at 00:21, wrote: > On 14/02/2017 22:47, Tamas K Lengyel wrote: >> (XEN) Switched to APIC driver x2apic_cluster. >> (XEN) XSM Framework v1.0.0 initialized >> (XEN) Flask: 128 avtab hash slots, 394 rules. >> (XEN) Flask: 128 avtab hash slots, 394 rules. >>

[Xen-devel] [PATCH v3 3/8] hw: Default -drive to if=none instead of ide when ide cannot work

Block backends defined with -drive if=ide are meant to be picked up by machine initialization code: a suitable frontend gets created and wired up automatically. if=ide drives not picked up that way can still be used with -device as if they had if=none, but that's unclean and best avoided. Unused

Re: [Xen-devel] [PATCH v2 01/10] xen: sched: harmonize debug dump output among schedulers.

On Thu, Feb 9, 2017 at 1:58 PM, Dario Faggioli wrote: > Information we currently print for idle pCPUs is I take it you meant "idle vCPUs here"? If so I can fix that up on check-in. Other than that: Reviewed-by: George Dunlap

Re: [Xen-devel] [PATCH v15 05/10] x86: add multiboot2 protocol support for EFI platforms

>>> On 14.02.17 at 19:38, wrote: > --- a/xen/arch/x86/boot/head.S > +++ b/xen/arch/x86/boot/head.S > @@ -394,10 +394,18 @@ __start: > > /* EFI IA-32 platforms are not supported. */ > cmpl$MULTIBOOT2_TAG_TYPE_EFI32,MB2_tag_type(%ecx) > +/* >

Re: [Xen-devel] [PATCH v2 02/10] xen: credit2: clear bit instead of skip step in runq_tickle()

On Thu, Feb 9, 2017 at 1:58 PM, Dario Faggioli wrote: > Since we are doing cpumask manipulation already, clear a bit > in the mask at once. Doing that will save us an if, later in > the code. > > No functional change intended. > > Signed-off-by: Dario Faggioli

Re: [Xen-devel] [PATCH 1/2] VMX: fix VMCS race on context-switch paths

On Tue, 2017-02-14 at 03:28 -0700, Jan Beulich wrote: > When __context_switch() is being bypassed during original context > switch handling, the vCPU "owning" the VMCS partially loses control of > it: It will appear non-running to remote CPUs, and hence their attempt > to pause the owning vCPU

Re: [Xen-devel] [PATCH v2 01/10] xen: sched: harmonize debug dump output among schedulers.

On Wed, 2017-02-15 at 10:17 +, George Dunlap wrote: > On Thu, Feb 9, 2017 at 1:58 PM, Dario Faggioli > wrote: > > > > Information we currently print for idle pCPUs is > > I take it you meant "idle vCPUs here"?   > Sort-of. What I actually meant is that we print

Re: [Xen-devel] [PATCH v2 03/10] xen: credit2: improve comments' style and definition of CSFLAG-s

On Thu, Feb 9, 2017 at 1:58 PM, Dario Faggioli wrote: > Most of the comments describing the meaning of the > vCPU flags used by the scheduler miss the 'wings' (or > have other minor style issues). > > Also, use 1U (instead of 1) as the base of shiftings. > > No

[Xen-devel] [PATCH v3 00/18] x86emul: MMX/SSEn support

This includes support for AVX counterparts of them as well as a few later SSE additions (basically covering the entire 0f-prefixed opcode space, but not the 0f38 and 0f3a ones, nor 3dnow). 1: catch exceptions occurring in stubs 2: support most memory accessing MMX/SSE{,2,3} insns 3: support

Re: [Xen-devel] [PATCH v2 04/10] xen: credit2: make accessor helpers inline functions instead of macros

On Thu, Feb 9, 2017 at 3:33 PM, Dario Faggioli wrote: > On Thu, 2017-02-09 at 07:36 -0700, Jan Beulich wrote: >> > > > On 09.02.17 at 14:58, wrote: >> > +/* CPU to runq_id macro */ >> > +static always_inline int c2r(const struct scheduler

Re: [Xen-devel] [PATCH] x86/VMX: sanitize VM86 TSS handling

At 01:13 -0700 on 15 Feb (1487121231), Jan Beulich wrote: > >>> On 14.02.17 at 18:35, wrote: > > At 06:37 -0700 on 13 Feb (1486967832), Jan Beulich wrote: > >> >>> On 13.02.17 at 14:19, wrote: > >> > -tss = mem_alloc(128, 128); > >> > -memset(tss, 0,

Re: [Xen-devel] [PATCH 1/2] VMX: fix VMCS race on context-switch paths

>>> On 15.02.17 at 11:27, wrote: > This is what I'm getting during the original test case (32 VMs reboot): > > (XEN) [ 1407.789329] Watchdog timer detects that CPU12 is stuck! > (XEN) [ 1407.795726] [ Xen-4.6.1-xs-local x86_64 debug=n Not tainted > ] > (XEN)

[Xen-devel] [PATCH v3 02/18] x86emul: support most memory accessing MMX/SSE{, 2, 3} insns

This aims at covering most MMX/SSEn/AVX instructions in the 0x0f-escape space with memory operands. Not covered here are irregular moves, converts, and {,U}COMIS{S,D} (modifying EFLAGS). Note that the distinction between simd_*_fp isn't strictly needed, but I've kept them as separate entries

[Xen-devel] [PATCH v3 03/18] x86emul: support MMX/SSE{,2,3} moves

Previously supported insns are being converted to the new model, and several new ones are being added. To keep the stub handling reasonably simple, integrate SET_SSE_PREFIX() into copy_REX_VEX(), at once switching the stubs to use an empty REX prefix instead of a double DS: one (no byte registers

Re: [Xen-devel] [PATCH 1/2] VMX: fix VMCS race on context-switch paths

On Wed, 2017-02-15 at 04:00 -0700, Jan Beulich wrote: > > > > On 15.02.17 at 11:27, wrote: > > > > This is what I'm getting during the original test case (32 VMs reboot): > > > > (XEN) [ 1407.789329] Watchdog timer detects that CPU12 is stuck! > > (XEN) [ 1407.795726]

[Xen-devel] [xen-unstable-coverity test] 105813: all pass - PUSHED

flight 105813 xen-unstable-coverity real [real] http://logs.test-lab.xenproject.org/osstest/logs/105813/ Perfect :-) All tests in this flight passed as required version targeted for testing: xen bdbc25b8722cc1e3921858530f8ac484892156d3 baseline version: xen

[Xen-devel] [PATCH v3 12/18] x86emul: add tables for 0f38 and 0f3a extension space

Convert the few existing opcodes so far supported. Signed-off-by: Jan Beulich --- v3: New. --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -43,6 +43,8 @@ #define SrcMask (7<<3) /* Generic ModRM decode. */ #define ModRM

[Xen-devel] [PATCH v3 11/18] x86emul: honor MMXEXT feature flag

This being a strict (MMX register only) subset of SSE, we can simply adjust the respective checks while making the new predicate look at both flags. Signed-off-by: Jan Beulich --- v3: New. --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++

[Xen-devel] [PATCH v3 13/18] x86emul: support SSSE3 insns

... and their AVX equivalents. Signed-off-by: Jan Beulich --- v3: New. --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -343,6 +343,8 @@ static const struct { uint8_t two_op:1; uint8_t vsib:1; } ext0f38_table[256] = { +

[Xen-devel] [xen-unstable test] 105804: tolerable FAIL - PUSHED

flight 105804 xen-unstable real [real] http://logs.test-lab.xenproject.org/osstest/logs/105804/ Failures :-/ but no regressions. Tests which are failing intermittently (not blocking): test-amd64-i386-libvirt-xsm 3 host-install(3) broken in 105799 pass in 105804

[Xen-devel] [PATCH v3 06/18] x86emul: support MMX/SSE/SSE2 insns with only register operands

This involves fixing a decode bug: VEX encoded insns aren't necessarily followed by a ModR/M byte. Signed-off-by: Jan Beulich --- v3: Simplify handling of extrq/insertq register forms. Use simd_0f_xmm label. v2: Correct {,v}pextrw operand descriptor. ---

[Xen-devel] [PATCH v2] libxl: correct xenstore entry for empty cdrom

Specifying an empty cdrom device will result in a Xenstore entry params = aio:(null) as the physical device path isn't existing. This lets a domain booted via OVMF hang as OVMF is checking for "aio:" only in order to detect the empty cdrom case. Use an empty string for the physical device path

[Xen-devel] [PATCH v3 07/18] x86emul: support {,V}{LD,ST}MXCSR

Signed-off-by: Jan Beulich --- v3: Re-base. --- a/tools/fuzz/x86_instruction_emulator/x86-insn-emulator-fuzzer.c +++ b/tools/fuzz/x86_instruction_emulator/x86-insn-emulator-fuzzer.c @@ -660,7 +660,7 @@ int LLVMFuzzerTestOneInput(const uint8_t }; int rc; -

[Xen-devel] [PATCH v3 14/18] x86emul: support SSE4.1 insns

... and their AVX equivalents. Signed-off-by: Jan Beulich --- v3: New. --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -214,6 +214,12 @@ enum simd_opsize { * - 32 bits with prefix F3 (scalar) */ simd_single_fp, +

[Xen-devel] [PATCH v3 16/18] x86emul: support PCLMULQDQ

... and its AVX equivalent. Signed-off-by: Jan Beulich --- v3: New. --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -387,6 +387,7 @@ static const struct { [0x22] = { .simd_size = simd_none }, [0x40 ... 0x41] = {

[Xen-devel] [PATCH v3 15/18] x86emul: support SSE4.2 insns

... and their AVX equivalents. Signed-off-by: Jan Beulich --- v3: New. --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -2542,6 +2542,149 @@ int main(int argc, char **argv) else printf("skipped\n"); +

Re: [Xen-devel] [PATCH 1/2] VMX: fix VMCS race on context-switch paths

On 15/02/17 08:37, Jan Beulich wrote: On 14.02.17 at 16:16, wrote: >> On 14/02/17 10:28, Jan Beulich wrote: >>> --- a/xen/arch/x86/hvm/vmx/vmcs.c >>> +++ b/xen/arch/x86/hvm/vmx/vmcs.c >>> @@ -552,6 +552,27 @@ static void vmx_load_vmcs(struct vcpu *v >>>

Re: [Xen-devel] [PATCH 2/2] x86: package up context switch hook pointers

>>> On 15.02.17 at 12:34, wrote: > On 15/02/17 08:42, Jan Beulich wrote: > On 14.02.17 at 16:26, wrote: >>> On 14/02/17 10:29, Jan Beulich wrote: @@ -2066,6 +2073,15 @@ static void __context_switch(void) per_cpu(curr_vcpu,

[Xen-devel] [PATCH v3 04/18] x86emul: support MMX/SSE/SSE2 converts

Note that other than most scalar instructions, vcvt{,t}s{s,d}2si do #UD when VEX.l is set on at least some Intel models. To be on the safe side, implement the most restrictive mode here for now when emulating an Intel CPU, and simply clear the bit when emulating an AMD one. Signed-off-by: Jan

[Xen-devel] [PATCH v3 05/18] x86emul: support {,V}{,U}COMIS{S,D}

Signed-off-by: Jan Beulich --- v3: Ignore VEX.l. Add fic.exn_raised constraint to invoke_stub() use. v2: Add missing RET to stub. Generate #UD (instead of simply failing) when VEX.l is disallowed. --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++

[Xen-devel] [PATCH v3 10/18] x86emul: test coverage for SSE/SSE2 insns

... and their AVX equivalents. Note that a few instructions aren't covered (yet), but those all fall into common pattern groups, so I would hope that for now we can do with what is there. MMX insns aren't being covered at all, as they're not easy to deal with: The compiler refuses to emit such

Re: [Xen-devel] [PATCH 1/2] VMX: fix VMCS race on context-switch paths

>>> On 15.02.17 at 12:13, wrote: > On Wed, 2017-02-15 at 04:00 -0700, Jan Beulich wrote: >> Similarly, when __context_switch() is being bypassed also on the second >> (switch-in) path, VMCS ownership may have been lost and hence needs >> re-establishing. Since there's no

Re: [Xen-devel] [PATCH 1/2] VMX: fix VMCS race on context-switch paths

>>> On 15.02.17 at 11:27, wrote: > This is what I'm getting during the original test case (32 VMs reboot): > > (XEN) [ 1407.789329] Watchdog timer detects that CPU12 is stuck! > (XEN) [ 1407.795726] [ Xen-4.6.1-xs-local x86_64 debug=n Not tainted > ] > (XEN)

Re: [Xen-devel] [PATCH 1/2] VMX: fix VMCS race on context-switch paths

On Wed, 2017-02-15 at 04:39 -0700, Jan Beulich wrote: > > > > On 15.02.17 at 11:27, wrote: > > > > This is what I'm getting during the original test case (32 VMs reboot): > > > > (XEN) [ 1407.789329] Watchdog timer detects that CPU12 is stuck! > > (XEN) [ 1407.795726]

Re: [Xen-devel] [PATCH v3 01/18] x86emul: catch exceptions occurring in stubs

>>> On 15.02.17 at 12:27, wrote: > On 15/02/17 11:06, Jan Beulich wrote: >> --- a/xen/arch/x86/x86_emulate/x86_emulate.c >> +++ b/xen/arch/x86/x86_emulate/x86_emulate.c >> @@ -604,14 +604,42 @@ do{ asm volatile ( >> #define __emulate_1op_8byte(_op, _dst, _eflags) >>

Re: [Xen-devel] RFC v2: Scope of Vulnerabilities for which XSAs are issued

George, I noticed that the blog post does not contain a link to the xen-devel@ discussion. I will add it Lars > On 15 Feb 2017, at 09:44, Jan Beulich wrote: > On 14.02.17 at 18:25, wrote: >> 4. The security team will only issue an advisory if

[Xen-devel] [PATCH v3 01/18] x86emul: catch exceptions occurring in stubs

Before adding more use of stubs cloned from decoded guest insns, guard ourselves against mistakes there: Should an exception (with the noteworthy exception of #PF) occur inside the stub, forward it to the guest. Since the exception fixup table entry can't encode the address of the faulting insn

[Xen-devel] [PATCH v3 09/18] x86emul/test: split generic and testcase specific parts

Both the build logic and the invocation have their blowfish specific aspects abstracted out here. Additionally - run native execution (if suitable) first (as that one failing suggests a problem with the to be tested code itself, in which case having the emulator have a go over it is kind of

[Xen-devel] [PATCH v3 08/18] x86emul: support {,V}MOVNTDQA

... as the only post-SSE2 move insn. Signed-off-by: Jan Beulich --- v3: Re-base. v2: Re-base. --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -2380,6 +2380,74 @@ int main(int argc, char **argv) else

[Xen-devel] [PATCH v3 18/18] x86emul: support SHA insns

Signed-off-by: Jan Beulich --- v3: New. --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -362,6 +362,7 @@ static const struct { [0x37 ... 0x3f] = { .simd_size = simd_packed_int }, [0x40] = { .simd_size = simd_packed_int },

[Xen-devel] [PATCH v3 17/18] x86emul: support AESNI insns

... and their AVX equivalents. Signed-off-by: Jan Beulich --- v3: New. --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -362,6 +362,8 @@ static const struct { [0x37 ... 0x3f] = { .simd_size = simd_packed_int }, [0x40] = {

Re: [Xen-devel] [PATCH] x86/VMX: sanitize VM86 TSS handling

At 01:18 -0700 on 15 Feb (1487121525), Jan Beulich wrote: > >>> On 14.02.17 at 18:33, wrote: > >> TBD: Do we really want to re-init the TSS every time we are about to > >> use it? > > > > No - I think we should init it when the guest writes the param(s) and > > leave it at

Re: [Xen-devel] [PATCH v3 01/18] x86emul: catch exceptions occurring in stubs

On 15/02/17 11:06, Jan Beulich wrote: > --- a/xen/arch/x86/x86_emulate/x86_emulate.c > +++ b/xen/arch/x86/x86_emulate/x86_emulate.c > @@ -604,14 +604,42 @@ do{ asm volatile ( > #define __emulate_1op_8byte(_op, _dst, _eflags) > #endif /* __i386__ */ > > +#ifdef __XEN__ > +# define

Re: [Xen-devel] [PATCH 2/2] x86: package up context switch hook pointers

On 15/02/17 08:42, Jan Beulich wrote: On 14.02.17 at 16:26, wrote: >> On 14/02/17 10:29, Jan Beulich wrote: >>> @@ -2066,6 +2073,15 @@ static void __context_switch(void) >>> per_cpu(curr_vcpu, cpu) = n; >>> } >>> >>> +/* >>> + * Schedule tail *should* be a

Re: [Xen-devel] [PATCH] x86/VMX: sanitize VM86 TSS handling

>>> On 15.02.17 at 12:21, wrote: > At 01:18 -0700 on 15 Feb (1487121525), Jan Beulich wrote: >> >>> On 14.02.17 at 18:33, wrote: >> >> TBD: Do we really want to re-init the TSS every time we are about to >> >> use it? >> > >> > No - I think we should init it

Re: [Xen-devel] [PATCH 1/2] VMX: fix VMCS race on context-switch paths

>>> On 15.02.17 at 12:48, wrote: > On Wed, 2017-02-15 at 04:39 -0700, Jan Beulich wrote: >> > > > On 15.02.17 at 11:27, wrote: >> > (XEN) [ 1408.075638] Xen call trace: >> > (XEN) [ 1408.079322][] vmx_vmcs_reload+0x32/0x50 >> > (XEN) [

[Xen-devel] Xen Security Advisory 207 - memory leak when destroying guest without PT devices

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Xen Security Advisory XSA-207 version 2 memory leak when destroying guest without PT devices UPDATES IN VERSION 2 Public release. ISSUE DESCRIPTION =

Re: [Xen-devel] Xen ARM - Exposing a PL011 to the guest

Hi Stefano, On 14 February 2017 at 03:14, Stefano Stabellini wrote: > On Mon, 13 Feb 2017, Bhupinder Thakur wrote: >> Hi Stefano, >> >> On 9 February 2017 at 05:40, Stefano Stabellini >> wrote: >> > On Wed, 8 Feb 2017, Bhupinder Thakur wrote: >>

Re: [Xen-devel] [PATCH] x86/VMX: sanitize VM86 TSS handling

>>> On 14.02.17 at 18:35, wrote: > At 06:37 -0700 on 13 Feb (1486967832), Jan Beulich wrote: >> >>> On 13.02.17 at 14:19, wrote: >> > -tss = mem_alloc(128, 128); >> > -memset(tss, 0, 128); >> > +tss = mem_alloc(TSS_SIZE, TSS_SIZE); >> >> tss =

Re: [Xen-devel] [PATCH] x86/VMX: sanitize VM86 TSS handling

>>> On 14.02.17 at 18:33, wrote: > Hi, > > At 06:19 -0700 on 13 Feb (1486966797), Jan Beulich wrote: >> The present way of setting this up is flawed: Leaving the I/O bitmap >> pointer at zero means that the interrupt redirection bitmap lives >> outside (ahead of) the allocated

Re: [Xen-devel] Xen ARM - Exposing a PL011 to the guest

Hi, On 15 February 2017 at 13:45, Bhupinder Thakur wrote: > Hi Stefano, > > On 14 February 2017 at 03:14, Stefano Stabellini > wrote: >> On Mon, 13 Feb 2017, Bhupinder Thakur wrote: >>> Hi Stefano, >>> >>> On 9 February 2017 at 05:40,

Re: [Xen-devel] [PATCH] x86/VMX: sanitize VM86 TSS handling

>>> On 14.02.17 at 16:48, wrote: > On 14/02/17 08:55, Jan Beulich wrote: > On 13.02.17 at 19:26, wrote: >>> On 13/02/17 13:19, Jan Beulich wrote: --- TBD: Do we really want to re-init the TSS every time we are about to

Re: [Xen-devel] [PATCH v2] x86/shadow: Correct guest behaviour when creating PTEs above maxphysaddr

>>> On 14.02.17 at 17:04, wrote: > On 13/02/17 12:36, Jan Beulich wrote: > On 13.02.17 at 12:00, wrote: >>> @@ -360,6 +361,21 @@ void paging_dump_vcpu_info(struct vcpu *v); >>> int paging_set_allocation(struct domain *d, unsigned int

Re: [Xen-devel] [PATCH 1/2] VMX: fix VMCS race on context-switch paths

>>> On 14.02.17 at 16:16, wrote: > On 14/02/17 10:28, Jan Beulich wrote: >> --- a/xen/arch/x86/hvm/vmx/vmcs.c >> +++ b/xen/arch/x86/hvm/vmx/vmcs.c >> @@ -552,6 +552,27 @@ static void vmx_load_vmcs(struct vcpu *v >> local_irq_restore(flags); >> } >> >> +void

Re: [Xen-devel] [PATCH 2/2] x86: package up context switch hook pointers

>>> On 14.02.17 at 16:26, wrote: > On 14/02/17 10:29, Jan Beulich wrote: >> @@ -2066,6 +2073,15 @@ static void __context_switch(void) >> per_cpu(curr_vcpu, cpu) = n; >> } >> >> +/* >> + * Schedule tail *should* be a terminal function pointer, but leave a >>

[Xen-devel] [PATCH v8 01/24] docs: create Cache Allocation Technology (CAT) and Code and Data Prioritization (CDP) feature document

This patch creates CAT and CDP feature document in doc/features/. It describes key points to implement L3 CAT/CDP and L2 CAT which is described in details in Intel SDM "INTEL® RESOURCE DIRECTOR TECHNOLOGY (INTEL® RDT) ALLOCATION FEATURES". Signed-off-by: Yi Sun --- v8:

[Xen-devel] [PATCH v8 00/24] Enable L2 Cache Allocation Technology & Refactor psr.c

Hi all, We plan to bring a new PSR (Platform Shared Resource) feature called Intel L2 Cache Allocation Technology (L2 CAT) to Xen. Besides the L2 CAT implementaion, we refactor the psr.c to make it more flexible to add new features and fulfill the principle, open for extension but closed for

[Xen-devel] [PATCH v8 03/24] x86: refactor psr: implement main data structures.

To construct an extendible framework, we need analyze PSR features and abstract the common things and feature specific things. Then, encapsulate them into different data structures. By analyzing PSR features, we can get below map. +--+--+--+ ->| Dom0 |

Re: [Xen-devel] [PATCH v3 2/3] xen/privcmd: Add IOCTL_PRIVCMD_DM_OP

> -Original Message- > From: Stefano Stabellini [mailto:sstabell...@kernel.org] > Sent: 14 February 2017 18:39 > To: Boris Ostrovsky > Cc: Paul Durrant ; xen-de...@lists.xenproject.org; > linux-ker...@vger.kernel.org; Stefano Stabellini

[Xen-devel] [distros-debian-squeeze test] 68561: tolerable trouble: broken/fail/pass

flight 68561 distros-debian-squeeze real [real] http://osstest.xs.citrite.net/~osstest/testlogs/logs/68561/ Failures :-/ but no regressions. Regressions which are regarded as allowable (not blocking): test-amd64-i386-i386-squeeze-netboot-pygrub 9 debian-di-install fail like 68536

Re: [Xen-devel] RFC v2: Scope of Vulnerabilities for which XSAs are issued

>>> On 14.02.17 at 18:25, wrote: > 4. The security team will only issue an advisory if there is a known > combination of software in which the vulnerability can be exploited. Considering the following text, perhaps "may" would end up a little less strict here than

[Xen-devel] [PATCH v8 17/24] x86: L2 CAT: implement CPU init and free flow.

This patch implements the CPU init and free flow for L2 CAT including L2 CAT initialization callback function. Signed-off-by: Yi Sun --- xen/arch/x86/psr.c| 72 +++ xen/include/asm-x86/psr.h | 1 + 2 files changed,

[Xen-devel] [PATCH v8 08/24] x86: refactor psr: set value: implement framework.

As set value flow is the most complicated one in psr, it will be divided to some patches to make things clearer. This patch implements the set value framework to show a whole picture firstly. It also changes domctl interface to make it more general. To make the set value flow be general and can

[Xen-devel] [PATCH v8 18/24] x86: L2 CAT: implement get hw info flow.

This patch implements get HW info flow for L2 CAT including L2 CAT callback function. Signed-off-by: Yi Sun --- xen/arch/x86/psr.c | 16 xen/arch/x86/sysctl.c | 15 +++ xen/include/asm-x86/psr.h | 1 +

[Xen-devel] [PATCH v8 06/24] x86: refactor psr: implement get hw info flow.

This patch implements get HW info flow including L3 CAT callback function. It also changes sysctl interface to make it more general. With this patch, 'psr-hwinfo' can work for L3 CAT. Signed-off-by: Yi Sun Reviewed-by: Konrad Rzeszutek Wilk

[Xen-devel] [PATCH v8 12/24] x86: refactor psr: set value: implement write msr flow.

Continue with previous patch: 'x86: refactor psr: set value: implement cos id picking flow.' We have got all features values and COS ID to set. Then, we write MSRs of all features except the setting value is same as original value. Till now, set value process is completed. Signed-off-by: Yi Sun

[Xen-devel] [PATCH v8 15/24] x86: refactor psr: implement get value flow for CDP.

This patch implements L3 CDP get value callback function. With this patch, 'psr-cat-show' can work for L3 CDP. Signed-off-by: Yi Sun --- xen/arch/x86/psr.c | 16 1 file changed, 16 insertions(+) diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c

[Xen-devel] [PATCH v8 13/24] x86: refactor psr: implement CPU init and free flow for CDP.

This patch implements the CPU init and free flow for CDP including L3 CDP initialization callback function. Signed-off-by: Yi Sun --- xen/arch/x86/psr.c | 104 + 1 file changed, 98 insertions(+), 6 deletions(-) diff

[Xen-devel] [PATCH v8 09/24] x86: refactor psr: set value: assemble features value array.

Only can one COS ID be used by one domain at one time. That means all enabled features' COS registers at this COS ID are valid for this domain at that time. When user updates a feature's value, we need make sure all other features' values are not affected. So, we firstly need assemble an array

[Xen-devel] [PATCH v8 14/24] x86: refactor psr: implement get hw info flow for CDP.

This patch implements get HW info flow for CDP including L3 CDP callback function. It also changes sysctl function to make it work for CDP. With this patch, 'psr-hwinfo' can work for L3 CDP. Signed-off-by: Yi Sun --- xen/arch/x86/psr.c| 18 ++

[Xen-devel] [PATCH v8 02/24] x86: refactor psr: remove L3 CAT/CDP codes.

The current cache allocation codes in psr.c do not consider future features addition and are not friendly to extend. To make psr.c be more flexible to add new features and fulfill the program principle, open for extension but closed for modification, we have to refactor the psr.c: 1. Analyze

[Xen-devel] [PATCH v8 07/24] x86: refactor psr: implement get value flow.

This patch implements get value flow including L3 CAT callback function. It also changes domctl interface to make it more general. With this patch, 'psr-cat-show' can work for L3 CAT but not for L3 code/data which is implemented in patch "x86: refactor psr: implement get value flow for CDP.".

[Xen-devel] [PATCH v8 04/24] x86: refactor psr: implement CPU init and free flow.

This patch implements the CPU init and free flow including L3 CAT initialization and feature list free. Signed-off-by: Yi Sun --- v8: - remove unused parameter of psr_cpu_prepare. - add comments in cpu_fini_work. - coding style fix. --- xen/arch/x86/cpuid.c

[Xen-devel] [PATCH v8 23/24] tools: L2 CAT: support set cbm for L2 CAT.

This patch implements the xl/xc changes to support set CBM for L2 CAT. The new level option is introduced to original CAT setting command in order to set CBM for specified level CAT. - 'xl psr-cat-cbm-set' is updated to set cache capacity bitmasks(CBM) for a domain according to input cache

[Xen-devel] [PATCH v8 11/24] x86: refactor psr: set value: implement cos id picking flow.

Continue with previous patch: 'x86: refactor psr: set value: implement cos finding flow.' If fail to find a COS ID, we need pick a new COS ID for domain. Only COS ID that ref[COS_ID] is 1 or 0 can be picked to input a new set feature values. Signed-off-by: Yi Sun ---

[Xen-devel] [PATCH v8 16/24] x86: refactor psr: implement set value callback functions for CDP.

This patch implements L3 CDP set value related callback functions. With this patch, 'psr-cat-cbm-set' command can work for L3 CDP. Signed-off-by: Yi Sun --- v8: - modify 'l3_cdp_write_msr' to 'void'. --- xen/arch/x86/psr.c | 118

[Xen-devel] [PATCH v8 19/24] x86: L2 CAT: implement get value flow.

This patch implements L2 CAT get value callback function and interface in domctl. Signed-off-by: Yi Sun --- xen/arch/x86/domctl.c | 7 +++ xen/arch/x86/psr.c | 12 xen/include/public/domctl.h | 1 + 3 files changed, 20 insertions(+)

[Xen-devel] [PATCH v8 24/24] docs: add L2 CAT description in docs.

This patch adds L2 CAT description in related documents. Signed-off-by: He Chen Signed-off-by: Yi Sun Acked-by: Wei Liu --- docs/man/xl.pod.1.in | 25 ++--- docs/misc/xl-psr.markdown | 10

[Xen-devel] [PATCH v8 21/24] tools: L2 CAT: support get HW info for L2 CAT.

This patch implements xl/xc changes to support get HW info for L2 CAT. 'xl psr-hwinfo' is updated to show both L3 CAT and L2 CAT info. Example(on machine which only supports L2 CAT): Cache Monitoring Technology (CMT): Enabled : 0 Cache Allocation Technology (CAT): L2 Socket ID : 0

[Xen-devel] [PATCH v8 22/24] tools: L2 CAT: support show cbm for L2 CAT.

This patch implements changes in xl/xc changes to support showing CBM of L2 CAT. The new level option is introduced to original CAT showing command in order to show CBM for specified level CAT. - 'xl psr-cat-show' is updated to show CBM of a domain according to input cache level. Examples:

[Xen-devel] [PATCH v8 05/24] x86: refactor psr: implement Domain init/free and schedule flows.

This patch implements the Domain init/free and schedule flows. Signed-off-by: Yi Sun Reviewed-by: Konrad Rzeszutek Wilk --- xen/arch/x86/psr.c | 62 +- 1 file changed, 61 insertions(+), 1

[Xen-devel] [PATCH v8 10/24] x86: refactor psr: set value: implement cos finding flow.

Continue with patch: 'x86: refactor psr: set value: assemble features value array' We can try to find if there is a COS ID on which all features' COS registers values are same as the array assembled before. Signed-off-by: Yi Sun --- xen/arch/x86/psr.c | 93

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