This patch enables the cpufreq driver support to Hygon Family 18h CPU:
- It recognize Hygon's boost state in boost_state(),
boost_set_msr(), extract_msr() functions.
- It also add SMBUS support for Hygon Family 18h in
amd_freq_sensitivity_init().
Signed-off-by: Pu Wen
---
drivers/cpufreq
This patch enables the ACPI driver support to Hygon Family 18h CPU:
- Add Hygon support in power_saving_mwait_init().
- Add Hygon support in lapic_timer_state_broadcast().
Signed-off-by: Pu Wen
---
drivers/acpi/acpi_pad.c | 1 +
drivers/acpi/processor_idle.c | 1 +
2 files changed, 2
This patch enables the X86 MCE infrastructure support to Hygon
Family 18h CPU:
- It enable Hygon check in __mcheck_cpu_init_early(), print_mce()
and mce_usable_address() etc.
Signed-off-by: Pu Wen
---
arch/x86/kernel/cpu/mcheck/mce-severity.c | 3 ++-
arch/x86/kernel/cpu/mcheck/mce.c
This patch enables the x86 KVM support to Hygon Family 18h CPU:
- Add Hygon CPU VENDOR ID macro for KVM.
- Add SVM support in cpu_has_svm().
- Add support in em_syscall_is_enabled().
Signed-off-by: Pu Wen
---
arch/x86/include/asm/kvm_emulate.h | 4
arch/x86/include/asm/virtext.h | 5
This patch enables the Xen Hypervisor support to Hygon
Family 18h CPU:
- Add Hygon support in Xen PMU arch init codes.
- Add Hygon support in PMU MSR read/write codes.
- Add Hygon support in read PMC codes.
Signed-off-by: Pu Wen
---
arch/x86/xen/pmu.c | 12
1 file changed, 8
xfreq_mode().
Signed-off-by: Pu Wen
---
tools/power/cpupower/utils/cpufreq-info.c | 6 --
tools/power/cpupower/utils/helpers/cpuid.c | 6 --
tools/power/cpupower/utils/helpers/helpers.h| 2 +-
tools/power/cpupower/utils/idle_monitor/mperf_monitor.c | 3 ++
in determine_memory_type(), per_family_init()
and scrub rate codes.
- Add X86_VENDOR_HYGON in amd64_cpuids[].
Signed-off-by: Pu Wen
---
drivers/edac/amd64_edac.c | 20 +++-
drivers/edac/amd64_edac.h | 4
drivers/edac/mce_amd.c| 4 +++-
3 files changed, 26 insertions(+), 2
_play_dead().
- MTRR for X86
- Add MTRR enablement for Hygon processor.
- NMI watchdog for X86
- Add Hygon support in nmi_perfctr_msr_to_bit() and
nmi_evntsel_msr_to_bit().
Signed-off-by: Pu Wen
---
arch/x86/include/asm/processor.h | 3 ++-
arch/x86/kernel/alternative.c | 4
to mitigate Spectre V2 Retpoline
vulnerability.
- Add Hygon's processor with no meltdown support in cpu_no_meltdown array.
Signed-off-by: Pu Wen
---
arch/x86/include/asm/nospec-branch.h | 4 ++--
arch/x86/kernel/cpu/bugs.c | 30 --
arch/x86/kernel/cpu/common.c
in pirq_routers arrays.
- Add Hygon support in amd_postcore_init(), early_root_info_init().
- APIC for X86
- Add Hygon support in modern_apic() and sync_Arb_IDs() as Hygon
processors are modern processors.
- Add Hygon support in detect_init_API().
Signed-off-by: Pu Wen
---
arch/x86/kernel
To make Xen work correctly on Hygon platforms, reuse AMD's Xen support
code path and add vendor check for Hygon along with AMD.
Signed-off-by: Pu Wen
---
arch/x86/xen/pmu.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen
gon.c for Dhyana CPU
initialization to reduce long-term maintenance effort.
Pu Wen (17):
x86/cpu: create Dhyana init file and register new cpu_dev to system
x86/cache: get cache size/leaves and setup cache cpumap for Dhyana
x86/mtrr: get MTRR number and support TOP_MEM2
x86/smpboot:
On 2018/8/12 21:26, Boris Ostrovsky wrote:
On 08/12/2018 04:55 AM, Juergen Gross wrote:
On 11/08/18 16:34, Boris Ostrovsky wrote:
On 08/11/2018 09:29 AM, Pu Wen wrote:
bool pmu_msr_read(unsigned int msr, uint64_t *val, int *err)
{
- if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD
On 2018/8/11 22:34, Boris Ostrovsky wrote:
On 08/11/2018 09:29 AM, Pu Wen wrote:
To make Xen work correctly on Hygon platforms, reuse AMD's Xen support
code path and add vendor check for Hygon along with AMD.
Signed-off-by: Pu Wen
---
arch/x86/xen/pmu.c | 15 ---
1 file changed
s.
- Rework patch descriptions.
- Create a separated arch/x86/kernel/cpu/hygon.c for Dhyana CPU
initialization to reduce long-term maintenance effort.
Pu Wen (16):
x86/cpu: create Dhyana init file and register new cpu_dev to system
x86/cache: get cache size/leaves and setup cache cpum
of kernel Hygon use the lagacy and safe versions of MSR
access. It works fine when VPMU enabled in Xen on Hygon platforms by
testing with perf.
Signed-off-by: Pu Wen
---
arch/x86/xen/pmu.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen
of kernel Hygon use the lagacy and safe versions of MSR
access. It works fine when VPMU enabled in Xen on Hygon platforms by
testing with perf.
Reviewed-by: Boris Ostrovsky
Signed-off-by: Pu Wen
---
arch/x86/xen/pmu.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git
on to reduce long-term maintenance effort.
Pu Wen (16):
x86/cpu: create Dhyana init file and register new cpu_dev to system
x86/cache: get cache size/leaves and setup cache cpumap for Dhyana
x86/mtrr: get MTRR number and support TOP_MEM2
x86/smpboot: smp init nodelay and no flush caches before s
Enable ACPI cpufreq driver support for Hygon by adding family ID check
along with AMD.
As Hygon platforms have SMBus device(PCI device ID 0x790b), enable Hygon
support to function amd_freq_sensitivity_init().
Signed-off-by: Pu Wen
---
drivers/cpufreq/acpi-cpufreq.c | 11
RRs, then cleared to 0 for operation.
The number of variable MTRRs for Hygon is 2 as AMD's.
Signed-off-by: Pu Wen
---
arch/x86/kernel/cpu/mtrr/cleanup.c | 3 ++-
arch/x86/kernel/cpu/mtrr/generic.c | 3 ++-
arch/x86/kernel/cpu/mtrr/mtrr.c| 2 +-
3 files changed, 5 insertions(+), 3 deletions(-)
diff --
Hygon Dhyana CPU has the SVM feature as AMD family 17h does.
Add Hygon support in the KVM infrastructure.
Signed-off-by: Pu Wen
---
arch/x86/include/asm/kvm_emulate.h | 4
arch/x86/include/asm/virtext.h | 5 +++--
arch/x86/kvm/emulate.c | 11 ++-
3 files changed
Hygon PMU arch is similar to AMD Family 17h. To support Hygon PMU, the
initialization flow for it just call amd_pmu_init() and change PMU name
to "HYGON". To share AMD's flow, add code check for Hygon family ID 18h
to run the code path of AMD family 17h in core/uncore functions.
Signed-
The ideal_nops for Dhyana processors should be p6_nops.
Signed-off-by: Pu Wen
---
arch/x86/kernel/alternative.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index a481763..8f4925b 100644
--- a/arch/x86/kernel/alternative.c
To make Xen work correctly on Hygon platforms, reuse AMD's Xen support
code path and add vendor check for Hygon along with AMD.
Signed-off-by: Pu Wen
---
arch/x86/xen/pmu.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c
Hygon machine check arch is similar to AMD family 17h. To enable the MCE
infrastructure support, add CPU vendor check for Hygon to share the code
path of AMD.
Add hygon mce init function mce_hygon_feature_init() to minimize further
maintenance effort.
Signed-off-by: Pu Wen
---
arch/x86/include
To make AMD64 MCE and EDAC drivers working on Hygon platforms, add Hygon
vendor check for them. Also Hygon PCI Device ID DF_F0/DF_F6(0x1460/0x1466)
of Host bridge is needed for these drivers. And support Dhyana processors
by using AMD 0x17 codes.
Signed-off-by: Pu Wen
---
drivers/edac
b_misc_ids[], hygon_nb_link_ids[].
To enable Hygon north bridge support, add new variable root_ids, and
assign its value based on whether CPU vendor is AMD or Hygon. Modify
the CONFIG_AMD_NB to depends on either AMD or Hygon.
Add Hygon support in amd_postcore_init(), early_root_info_init().
Signed-
Hygon processors use modern APIC, so just return in modern_apic() and
sync_Arb_IDs(). And should break in switch case in detect_init_API().
Signed-off-by: Pu Wen
---
arch/x86/kernel/apic/apic.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel
Dhyana use no delay in smp_quirk_init_udelay(), and return in
mwait_play_dead() as AMD does.
Signed-off-by: Pu Wen
---
arch/x86/kernel/smpboot.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index db9656e..26cb2c9
.
v1->v2:
- Rebased on 4.18-rc6 and tested against it.
- Split the patchset to small series of patches.
- Rework patch descriptions.
- Create a separated arch/x86/kernel/cpu/hygon.c for Dhyana CPU
initialization to reduce long-term maintenance effort.
Pu Wen (17):
x86/cpu: create Dhy
Hygon Dhyana shares similar perfctr arch with AMD family 17h.
It returns the bit offset of the performance counter register and the
event selection register for Hygon CPU in the similar way as AMD does.
Signed-off-by: Pu Wen
---
arch/x86/kernel/cpu/perfctr-watchdog.c | 8
1 file
For Dhyana processors have NONSTOP TSC feature, so enable the support
to ACPI driver.
Signed-off-by: Pu Wen
---
drivers/acpi/acpi_pad.c | 1 +
drivers/acpi/processor_idle.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c
index
a separated Kconfig entry(CPU_SUP_
HYGON) for Dhyana CPU in kernel config setup.
Signed-off-by: Pu Wen
---
MAINTAINERS | 6 +
arch/x86/Kconfig.cpu | 13 ++
arch/x86/include/asm/processor.h | 3 +-
arch/x86/kernel/cpu/Makefile | 1 +
arch/x86/kernel/cpu/hygon.c
vulnerability as AMD's,
so add exception in array cpu_no_meltdown[] for it.
Signed-off-by: Pu Wen
---
arch/x86/include/asm/nospec-branch.h | 4 ++--
arch/x86/kernel/cpu/bugs.c | 28 +++-
arch/x86/kernel/cpu/common.c | 1 +
3 files changed, 18 insertions(+), 15
().
Also add cacheinfo_hygon_init_llc_id() and init_hygon_cacheinfo()
functions to initialize Dhyana cache info. Setup cache cpumap in
the same way as AMD does.
Signed-off-by: Pu Wen
---
arch/x86/include/asm/cacheinfo.h | 1 +
arch/x86/kernel/cpu/cacheinfo.c | 31
t.
- Split the patchset to small series of patches.
- Rework patch descriptions.
- Create a separated arch/x86/kernel/cpu/hygon.c for Dhyana CPU
initialization to reduce long-term maintenance effort.
Pu Wen (16):
x86/cpu: Create Hygon Dhyana architecture support file
x86/cpu: Get cache in
).
In this version of kernel Hygon use the lagacy and safe versions of MSR
access. It works fine when VPMU enabled in Xen on Hygon platforms by
testing with perf.
Reviewed-by: Boris Ostrovsky
Signed-off-by: Pu Wen
---
arch/x86/xen/pmu.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions
).
In this version of kernel Hygon use the legacy and safe version of MSR
access. It works fine when VPMU enabled in Xen on Hygon platform by
testing with perf.
Signed-off-by: Pu Wen
Reviewed-by: Boris Ostrovsky
---
arch/x86/xen/pmu.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff
r Dhyana CPU
initialization to reduce long-term maintenance effort.
Pu Wen (16):
x86/cpu: Create Hygon Dhyana architecture support file
x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana
x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number
x86/smpboot: SMP init no delay and not f
/* clear exceptions */
> "ffree %%st(7)\n\t" /* clear stack tag */
> "fildl %0" /* load to clear state */
It seems that the functions fpu_fxrstor and fpu_fxsave have the same
problem, even though they are not cal
On 2018/12/28 6:41, Andrew Cooper wrote:
> On 20/12/2018 13:15, Pu Wen wrote:
>> The Hygon Dhyana CPU don't save/restore FDP/FIP/FOP unless an exception
>> is pending. So add support for it in the function xrstor.
>
> Really?
>
> Zen was the first AMD process
gt; At the very least here I think you want to change to switch().
I think there is no need to change if() to switch(), because if() looks
concise enough here. Also the change will generate a bigger patch.
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es, if Hygon directly followed AMD's cases, the
insertions are placed above the respective AMD ones.
If Hygon used its own cases, such as in calc_ler_msr, the new cases
are placed below the AMD ones.
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_flags quirkflag = 0;
+
+if (ci->x86_vendor != X86_VENDOR_HYGON)
+quirkflag = mcequirk_lookup_amd_quirkdata(ci);
Is the modification OK?
Also add mcequirk_lookup_hygon_quirkdata() is another solution, even
though it will do nothing at the moment.
--
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Pu Wen
- please don't, insert the new ones after AMD's.
OK. Will insert the new ones after AMD's in next version patch set.
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Add Hygon Dhyana support to handle HyperTransport range.
Also loading a nul selector does not clear bases and limits on Hygon
CPUs, so add Hygon Dhyana support to the function preload_segment.
Signed-off-by: Pu Wen
---
xen/arch/x86/dom0_build.c | 3 ++-
xen/arch/x86/domain.c | 9
to write the load-store configuration(LS_CFG) MSR, so add
new case in write_msr to handle this situation.
Signed-off-by: Pu Wen
---
xen/arch/x86/pv/emul-priv-op.c | 29 -
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/xen/arch/x86/pv/emul-priv-op.c b
The Hygon Dhyana CPU don't save/restore FDP/FIP/FOP unless an exception
is pending. So add support for it in the function xrstor.
Signed-off-by: Pu Wen
---
xen/arch/x86/xstate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/xstate.c b/xen/arch/x86
The Hygon Dhyana family 18h processor shares the same cpuid leaves as the
AMD family 17h one. So add Hygon Dhyana support to caculate the cpuid
policies as the AMD CPU does.
Signed-off-by: Pu Wen
---
xen/arch/x86/cpuid.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff
Add Hygon Dhyana support to caculate the cpuid policies for creating PV
or HVM guest by using the code path of AMD.
Signed-off-by: Pu Wen
---
tools/libxc/xc_cpuid_x86.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc
The Hygon Dhyana processor has the methold to get the last exception
source IP from MSR_01DD. So add support for it if the boot param
ler is true.
Signed-off-by: Pu Wen
---
xen/arch/x86/traps.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
Add Hygon Dhyana support to update cpuid info for creating PV guest.
Signed-off-by: Pu Wen
---
xen/arch/x86/domctl.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index aa8ad19..a64c724 100644
--- a/xen/arch/x86
X86_VENDOR_HYGON
for system recognition.
Signed-off-by: Pu Wen
---
xen/arch/x86/cpu/Makefile | 1 +
xen/arch/x86/cpu/common.c | 1 +
xen/arch/x86/cpu/cpu.h| 1 +
xen/arch/x86/cpu/hygon.c | 296 ++
xen/include/asm-x86/x86
The Hygon Dhyana CPU supports the MSR way to get TOP_MEM2. So add Hygon
Dhyana support to print the value of TOP_MEM2.
Signed-off-by: Pu Wen
---
xen/arch/x86/cpu/mtrr/generic.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/cpu/mtrr/generic.c b/xen/arch
The PMU architecture for the Hygon Dhyana CPU is similar to the AMD
family 17h one. To support it, add Hygon Dhyana support in the similar
way as AMD does.
Signed-off-by: Pu Wen
---
xen/arch/x86/cpu/vpmu.c | 2 ++
xen/arch/x86/cpu/vpmu_amd.c | 2 ++
2 files changed, 4 insertions(+)
diff
The Hygon Dhyana CPU has the same speculative execution as AMD family
17h, so share AMD Retpoline and PTI mitigation code with Hygon Dhyana.
Signed-off-by: Pu Wen
---
xen/arch/x86/spec_ctrl.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/spec_ctrl.c b
The IOMMU architecture for the Hygon Dhyana CPU is similar to the AMD
family 17h one. So add Hygon Dhyana support to it by sharing the code
path of AMD.
Signed-off-by: Pu Wen
---
xen/include/asm-x86/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/xen/include/asm-x86/iommu.h b/xen
endor type
(X86_VENDOR_HYGON, with value of 5), and share most of the codes with
AMD family 17h.
This patch series have been applied and tested successfully on Hygon
Dhyana processor. Also tested on AMD EPYC (family 17h) processor, it
works fine and makes no harm to the existing codes.
Pu Wen (15):
Add Hygon Dhyana support to use modern APIC.
Signed-off-by: Pu Wen
---
xen/arch/x86/apic.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index 2a24326..004d685 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -92,6 +92,11
Add Hygon Dhyana support to the acpi cpufreq subsystem by using the code
path of AMD.
Signed-off-by: Pu Wen
---
xen/arch/x86/acpi/cpu_idle.c | 3 ++-
xen/arch/x86/acpi/cpufreq/cpufreq.c | 6 --
xen/arch/x86/acpi/cpufreq/powernow.c | 3 ++-
3 files changed, 8 insertions(+), 4
The machine check architecture for Hygon Dhyana CPU is similar to the
AMD family 17h one. Add vendor checking for Hygon Dhyana to share the
code path of AMD family 17h.
Signed-off-by: Pu Wen
---
xen/arch/x86/cpu/common.c | 3 ++-
xen/arch/x86/cpu/mcheck/amd_nonfatal.c | 5
s here in Dhyana
cases.
Since both of Zen and Dhyana support C001_020X MSRs. If use the C001_020X
is preferred, we will try to modify the related codes and create a patch.
Also the Linux Xen PMU driver may need to be updated to use these MSRs.
--
Regards,
Pu Wen
___
al old architectures, so I'm afraid that there are sufficient
motivations to keep a clear new processor init flow.
2) Beneficial for the future maintaining. AMD and Hygon may maintain their
respective architecture related codes with no interaction with each
other.
For these reasons, we choose to keep the architecture initialization codes
in hygon.c.
Thx.
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On 2018/12/21 21:34, Boris Ostrovsky wrote:
> On 12/21/18 5:02 AM, Pu Wen wrote:
>> On 2018/12/20 22:25, Boris Ostrovsky wrote:
>> ...
>>>> diff --git a/xen/arch/x86/cpu/vpmu_amd.c b/xen/arch/x86/cpu/vpmu_amd.c
>>>> index 5efc39b..e9f0a5c 100644
>>&g
On 2018/12/28 5:11, Andrew Cooper wrote:
> On 26/12/2018 11:42, Pu Wen wrote:
>> On 2018/12/21 18:20, Andrew Cooper wrote:
>>> Is there anything which is actually unique to Hygon here? I ask,
>>> because this looks like a lot of duplicate code, considering that the
>
;v2:
- Rebased on 4.18-rc6 and tested against it.
- Split the patch set to small series of patches.
- Rework patch descriptions.
- Create a separated arch/x86/kernel/cpu/hygon.c for Dhyana CPU
initialization to reduce long-term maintenance effort.
Pu Wen (16):
x86/cpu: Create Hygon Dhya
).
In this version of kernel Hygon use the legacy and safe version of MSR
access. It works fine when VPMU enabled in Xen on Hygon platform by
testing with perf.
Signed-off-by: Pu Wen
Reviewed-by: Boris Ostrovsky
---
arch/x86/xen/pmu.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff
committing, and with them in place
Acked-by: Jan Beulich
Thanks.
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directly return false in the function probe_cpuid_faulting() if
!cpu_has_hypervisor.
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of int.
>
> Why in front of int? The old line of code here shows the canonical
> ordering we use.
Sorry, after int. :)
By the way, how about the patch 01/15 of this series?
If it's fine, could you please offer Acked-by tag for it?
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opped when reading the MSR_INTEL_PLATFORM_INFO instead of
producing #GP(0).
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On 2019/4/2 20:16, Andrew Cooper wrote:
> On 30/03/2019 10:42, Pu Wen wrote:
>> +static const struct cpu_dev hygon_cpu_dev = {
>> +.c_vendor = "Hygon",
>> +.c_ident= { "HygonGenuine" },
>> +.c_early_init = early
01/15 should rebase over
http://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=e72309ffbe7c4e507649c74749f130cda691131c
.
So I think I'll rework the patch first.
Thx.
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https:
On 2019/4/2 23:14, Andrew Cooper wrote:
On 30/03/2019 10:40, Pu Wen wrote:
This patch series have been applied and tested successfully on Hygon
Dhyana processor, also been tested on AMD EPYC (family 17h) processor.
It works fine and makes no harm to the existing code.
Reference:
[1]
https
ve. Andrew - you've tried to boot Xen on a
Rome already. Iirc you said it crashed, but did it perhaps get to
(and past) this point?
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l hypervisor.
I think this is the most important reason. Previously I only considered
to run Hygon Xen on bare hardware, which is the most important usage for
a server processor. To match all the using cases I'll add the checking
you mentioned above.
--
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Pu Wen
_
ero.
I think it's a good idea to move the default case into the shared
function, which would like:
static int common_init(void)
{
unsigned int i;
if (!num_counters) {
printk(XENLOG_WARNING "VPMU: Unsupported CPU family %#x\n",
current_cpu_data.x86);
return false;
>
> Right, plus perhaps said AMD addition, unless Andrew objects to it
> for some reason.
Then it would be like this:
if ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ||
boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
!cpu_has_hypervisor)
return false;
Andrew, any objections?
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fine to me.
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unsigned long long value;
...
>> +if (cpu_has(c, X86_FEATURE_EFRO)) {
>> +rdmsr(MSR_K7_HWCR, l, h);
>> +l |= (1 << 27); /* Enable read-only APERF/MPERF bit */
>> +wrmsr(MSR_K7_HWCR, l, h);
>> +}
>
> ... "value" and rdmsrl() / wrmsrl() here instead.
Will use rdmsrl()/wrmsrl() instead.
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Add Hygon Dhyana support to caculate the cpuid policies for creating PV
or HVM guest by using the code path of AMD.
Signed-off-by: Pu Wen
Acked-by: Wei Liu
---
tools/libxc/xc_cpuid_x86.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/tools/libxc
msr_safe instead.
- Remove wrmsr_hygon and use wrmsrl instead.
- Remove the unnecessary change to xstate.
- Refine some codes and comments.
- Add Acked-by from Jan Beulich for x86/traps.
- Add Acked-by from Wei Liu for tools/libxc.
Pu Wen (14):
x86/cpu: Create Hygon Dhyana architecture su
Add Hygon Dhyana support to handle HyperTransport range.
Also loading a nul selector does not clear bases and limits on Hygon
CPUs, so add Hygon Dhyana support to the function preload_segment.
Signed-off-by: Pu Wen
Acked-by: Jan Beulich
---
xen/arch/x86/dom0_build.c | 3 ++-
xen/arch/x86
Add Hygon Dhyana support to use modern APIC.
Signed-off-by: Pu Wen
Acked-by: Jan Beulich
---
xen/arch/x86/apic.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index 2a24326..004d685 100644
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
The IOMMU architecture for the Hygon Dhyana CPU is similar to the AMD
family 17h one. So add Hygon Dhyana support to it by sharing the code
path of AMD.
Signed-off-by: Pu Wen
Acked-by: Jan Beulich
---
xen/include/asm-x86/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/xen/include
The Hygon Dhyana family 18h processor shares the same cpuid leaves as
the AMD family 17h one. So add Hygon Dhyana support to caculate the
cpuid policies as the AMD CPU does.
Signed-off-by: Pu Wen
Acked-by: Jan Beulich
---
xen/arch/x86/cpuid.c | 10 +++---
1 file changed, 7 insertions(+), 3
The machine check architecture for Hygon Dhyana CPU is similar to the
AMD family 17h one. Add vendor checking for Hygon Dhyana to share the
code path of AMD family 17h.
Signed-off-by: Pu Wen
Acked-by: Jan Beulich
---
xen/arch/x86/cpu/common.c | 3 ++-
xen/arch/x86/cpu/mcheck
-by: Pu Wen
Acked-by: Jan Beulich
---
xen/arch/x86/pv/emul-priv-op.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
index 3746e2a..c92f9dc 100644
--- a/xen/arch/x86/pv/emul-priv-op.c
+++ b/xen/arch
Add Hygon Dhyana support to update cpuid info for creating PV guest.
Signed-off-by: Pu Wen
Acked-by: Jan Beulich
---
xen/arch/x86/domctl.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 9bf2d08..19b7bdd
The Hygon Dhyana CPU supports the MSR way to get TOP_MEM2. So add Hygon
Dhyana support to print the value of TOP_MEM2.
Signed-off-by: Pu Wen
Acked-by: Jan Beulich
---
xen/arch/x86/cpu/mtrr/generic.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/cpu/mtrr
The Hygon Dhyana processor has the methold to get the last exception
source IP from MSR_01DD. So add support for it if the boot param
ler is true.
Signed-off-by: Pu Wen
Acked-by: Jan Beulich
---
xen/arch/x86/traps.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/xen/arch/x86
The Hygon Dhyana CPU has the same speculative execution as AMD family
17h, so share AMD Retpoline and PTI mitigation code with Hygon Dhyana.
Signed-off-by: Pu Wen
Acked-by: Jan Beulich
---
xen/arch/x86/spec_ctrl.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/xen
directly return false in the
function probe_cpuid_faulting().
Add a separate hygon_get_topology(), which calculate phys_proc_id from
AcpiId[6](see reference [1]).
Reference:
[1] https://git.kernel.org/tip/e0ceeae708cebf22c990c3d703a4ca187dc837f5
Signed-off-by: Pu Wen
---
xen/arch/x86/cpu
Add Hygon Dhyana support to the acpi cpufreq and cpuidle subsystems by
using the code path of AMD.
Signed-off-by: Pu Wen
Acked-by: Jan Beulich
---
xen/arch/x86/acpi/cpu_idle.c | 3 ++-
xen/arch/x86/acpi/cpufreq/cpufreq.c | 8 +---
xen/arch/x86/acpi/cpufreq/powernow.c | 3 ++-
3
the 15h definitions for them.
Signed-off-by: Pu Wen
---
xen/arch/x86/cpu/vpmu.c | 5
xen/arch/x86/cpu/vpmu_amd.c | 57 -
xen/include/asm-x86/vpmu.h | 1 +
3 files changed, 47 insertions(+), 16 deletions(-)
diff --git a/xen/arch/x86/cpu/vpmu.c b
On 2019/4/3 0:15, Jan Beulich wrote:
> On 02.04.19 at 18:00, wrote:
>> On 2019/4/2 23:14, Andrew Cooper wrote:
>>> On 30/03/2019 10:40, Pu Wen wrote:
>>>> This patch series have been applied and tested successfully on Hygon
>>>> Dhyana processor
it should be retained.
Okay, will retain the conditionals.
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the 15h definitions for them.
Signed-off-by: Pu Wen
Acked-by: Jan Beulich
---
xen/arch/x86/cpu/vpmu.c | 8 ++
xen/arch/x86/cpu/vpmu_amd.c | 61 -
xen/include/asm-x86/vpmu.h | 1 +
3 files changed, 52 insertions(+), 18 deletions(-)
diff --git
The Hygon Dhyana CPU has the same speculative execution as AMD family
17h, so share AMD Retpoline and PTI mitigation code with Hygon Dhyana.
Signed-off-by: Pu Wen
Acked-by: Jan Beulich
---
xen/arch/x86/spec_ctrl.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/xen
The machine check architecture for Hygon Dhyana CPU is similar to the
AMD family 17h one. Add vendor checking for Hygon Dhyana to share the
code path of AMD family 17h.
Signed-off-by: Pu Wen
Acked-by: Jan Beulich
---
xen/arch/x86/cpu/common.c | 3 ++-
xen/arch/x86/cpu/mcheck
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