[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: bd9e42e723aff3531b03614a56dfde450d2579da
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=bd9e42e723aff3531b03614a56dfde450d2579da

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: cfd8292ffa1c7702b2678245f37cd884f5f5e275
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=cfd8292ffa1c7702b2678245f37cd884f5f5e275

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: 8b742e6c590899f4f9ee53302a05e6a0a7ed7a46
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=8b742e6c590899f4f9ee53302a05e6a0a7ed7a46

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: 0e92aa9a793138296456c986d70bd964f464f2aa
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=0e92aa9a793138296456c986d70bd964f464f2aa

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: 89e1029f6c496e86498648abbdc356444c37d1a1
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=89e1029f6c496e86498648abbdc356444c37d1a1

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: fb2d85f4da4940b3738babdc1fed5c034002a2fd
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=fb2d85f4da4940b3738babdc1fed5c034002a2fd

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: 7b4f8e2b81d8c5b27cf061ee7df2e509c32e03b2
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=7b4f8e2b81d8c5b27cf061ee7df2e509c32e03b2

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: 205b3b5408e35be59742366ca4d9aadd8e64069b
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=205b3b5408e35be59742366ca4d9aadd8e64069b

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: c11ec778470198e64b7b1a9f6ce921c3a57b20e5
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=c11ec778470198e64b7b1a9f6ce921c3a57b20e5

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: fc6ff4c47d963c0fc96311cde792910c7323c2c9
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=fc6ff4c47d963c0fc96311cde792910c7323c2c9

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: 363487cb8d3f57d6f64e6edcc7911169b7b5433b
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=363487cb8d3f57d6f64e6edcc7911169b7b5433b

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: 189a041a0c8867a8495e212dc264ca3ed913b4d3
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=189a041a0c8867a8495e212dc264ca3ed913b4d3

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: 66dfba9aebce67adfe106c48a609f706a9b642ce
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=66dfba9aebce67adfe106c48a609f706a9b642ce

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: 7b4cedb99ea3bf7113092d7c4ad7c06a59a23756
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=7b4cedb99ea3bf7113092d7c4ad7c06a59a23756

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: 56eea9cc9088d701949b7b8d6e2ce1eb42ac1b26
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=56eea9cc9088d701949b7b8d6e2ce1eb42ac1b26

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: next
Commit: 145c86a8035db535cbffd54fe5625100aae66f54
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=145c86a8035db535cbffd54fe5625100aae66f54

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: arm64
Commit: 6cf61fcf6ee76cf5be2aaf0042ebb2a124a3d093
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=6cf61fcf6ee76cf5be2aaf0042ebb2a124a3d093

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: arm64
Commit: 42ed1574420c688b4acb5e21c2ec1adc3d16a1b3
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=42ed1574420c688b4acb5e21c2ec1adc3d16a1b3

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: arm64
Commit: d9a3077160e6c9a39839d9b22533b6e16445255d
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=d9a3077160e6c9a39839d9b22533b6e16445255d

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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[Xenomai-git] Philippe Gerum : cobalt/arm64: restrict unlocked switch to SMP

[git repository hosting]

Module: xenomai-3
Branch: arm64
Commit: d5ea33f3d9bf22e737100449b44694e7d5133b89
URL:
http://git.xenomai.org/?p=xenomai-3.git;a=commit;h=d5ea33f3d9bf22e737100449b44694e7d5133b89

Author: Philippe Gerum 
Date:   Thu Sep 17 11:43:50 2015 +0200

cobalt/arm64: restrict unlocked switch to SMP

Unlocked switching for Xenomai/ARM was specifically introduced for
improving the interrupt latency on low-end armv4/armv5 platforms with
VIVT caches.

The once massive overhead imposed on the MMU context switching code
for invalidating the cache is long gone with VIPT indexing, and
keeping IRQs off while switching the memory context on armv8 these
days is not an issue. Actually, the complexity of the code involved in
dealing with unlocked switching may overbalance the expected gain.

However, the mainline kernel implementation for ASID management in the
SMP case currently requires us to keep IRQs enabled when allocating a
new MM context over the Xenomai domain, just like it did for aarch32
during the 2.6.3x time frame until the IPI-based approach was
eventually dropped.

So, let's restrict unlocked switching to the SMP case, forcing it off
otherwise, in the hope we can drop it entirely in the future.

At this chance, CONFIG_IPIPE_WANT_PREEMPTIBLE_SWITCH moves to the
kernel area, where it actually belongs.

---

 kernel/cobalt/arch/arm64/Kconfig |   21 +
 1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/kernel/cobalt/arch/arm64/Kconfig b/kernel/cobalt/arch/arm64/Kconfig
index dc6485d..927c647 100644
--- a/kernel/cobalt/arch/arm64/Kconfig
+++ b/kernel/cobalt/arch/arm64/Kconfig
@@ -1,27 +1,8 @@
 source "kernel/xenomai/Kconfig"
 source "drivers/xenomai/Kconfig"
 
-menu "Machine/platform-specific options"
-
 config XENO_ARCH_UNLOCKED_SWITCH
-   bool "Unlocked context switch"
-   default y
-   help
-   The Cobalt core may allow non-atomic execution of the
-   machine-dependent context switching code, so that other CPUs
-   and/or local interrupts may execute concurrently.
-
-   This option reduces interrupt latency when costly cache and
-   TLB flushes are required to switch context.
-
-   You definitely want to enable that option on low-end ARM
-   platforms.
-endmenu
-
-config IPIPE_WANT_PREEMPTIBLE_SWITCH
-   bool
-   default y if XENO_ARCH_UNLOCKED_SWITCH
-   default n if !XENO_ARCH_UNLOCKED_SWITCH
+   def_bool IPIPE_WANT_PREEMPTIBLE_SWITCH
 
 config IPIPE_WANT_ACTIVE_MM
def_bool y


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