-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi Ian,
Thanks for getting back to me so quickly. I'm very glad to hear from you. > The demon core was released under GPL2 so feel free to leverage it > on those terms. Yes, that is very helpful to us. But it's not just about adhering to the license. We're also keen to try and help consolidate the various efforts that have been made. As you can see on the wiki page, there are many projects that have sprung up to run on a single device, and then been been forgotten. I'm keen for us to enable something more versatile that can be reused again and again across many devices, and something that is in the hands of a community, so that the burden to maintain the code doesn't fall on a single person. I think the sigrok community are well placed to take up that challenge. There are already several guys who have said they'd like to contribute. But I don't want to start yet another SUMP derived fork, without reaching out to people who've done previous work. Do you know if there's another crowd somewhere I should try and make contact with? > Note the current Logic Sniffer fpga (XCV250E) is very full. > Minor changes should be fine, but adding anything major will > doubtless be a problem. Yes, so we're hoping to be able to produce modular framework, where features can be selected or removed depending on the capability of the device. Also the most interesting devices can be bootstrapped at runtime, so that you can select from several firmware variants depending on what the user wants to do. For example I can imagine having a very simple firmware that has been optimized for ultra high speed sampling, and so it would need to be much simplified e.g. have a limited triggering capability. If the user wants to sample more slowly we can load a more featureful image having compression, and advanced triggers baked into it. For example in the RockyLogic devices, the vendor has managed to achieve sampling at 1GHz on a Spartan 3E! I believe they do this by using clever tricks with the 4 clock phases from a PLL, but that can only work if all the other bells and whistles are removed. > It was designed for maximum logic density on Xilinx fpga's only. > Many of the design choices won't port easily to other fpga vendors > (like Altera). Yes, I expect this to be a major challenge. On the plus side, there are already a couple of volunteers. One guy says he's got experience with this stuff. > > Now... not to dump on your idea, but you're going to face some > challenges. A couple points... > > First, the various vendors want to differentiate themselves. > Assuming similar advanced triggers, you should still expect > differing numbers of terms, range checks, edge checks, states, > etc... Mostly because of differing fpga flavors. Bigger parts = > more features. Yes, so we need to make these parametrically adjustable. > > Second, I based demon core on HP16550 style triggers. I doubt > HP/Agilent cares about an low volume open source project. > Commercial vendors however are viewed in an entirely different > light. I have no idea what HP/Agilent patents the demon core > infringes upon -- assuming any are still valid. Such concerns > will give commercial vendors pause. So this firmware isn't primarily for vendors to use - though they would be welcome to use it, but they are usually not interested, mainly because they've invested in firmwares of their own. It's application to logic analyser products is as an after-market open firmware, that will hopefully add extra features, and enable the device to be supported in sigrok. Where is becomes more interesting is when it is used on various low cost (<$50) FPGA dev boards that are available today. This project would enable any board with a (reasonable) FPGA on it to become a logic analyser (both for in-circuit use cases, or as a test tool). > In any case, I'll be happy to offer suggestions. Can't promise > I'll have the time to develop new logic though. Yes that would be very helpful. It seems like your knowledge on these would be very valuable. If you would like to join in, please do drop the #sigrok channel on freenode IRC. Best Regards Joel > > Cheers! -- Ian > > > > Joel Holdsworth wrote: > > Dear Ian, > > Sorry to write to you on your work e-mail. I've been struggling to > find any other contact details for you online. > > I'm writing to you from the sigrok open source project, which is a > project about building an open source software suite to support > all kinds of signal analysis devices including logic analyzers and > MSOs. > > We are in the early stages of exploring the possibility of building > a flexible/universal FPGA logic analyzer firmware. Our initial > thoughts are being assembled here: http://sigrok.org/wiki/Fpgalafw > > From my review of prexisting projects, it seems like your Demon > core for the OLS is one of the more mature projects, so me may end > up starting with this as a base, but I didn't want to do anything > without first talking to you. > > I wondered if you would you like to participate in this effort in > any way? Just hearing your thoughts or advice would be helpful, or > if you'd like to get fully involved that would also be great. > > So let me know if you have any thoughts about this. > > Best Regards Joel Holdsworth > > >> >> > -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBAgAGBQJRdrFzAAoJEIsWlGmq62IgceUH/0u0gqW5v9hboBkCtqJ8P6du 7KCT0PZGqmI7fZ92Gmf0ELo1Ll0q0WoQ8NnSBhJNwJ+4SLhYawXmL96tf3B3pY0j oieqQc2k1wbNTm+XeBJzoXVNfNT7aeBT5Cbszn0hPIKWhr4+btlz+2P0mtBgeN8/ ZCZV8uOpbWTVfr+WDb4IzYEs0HT05cP7xFue9ub8AJZto5ONg/nXlgbjIB1PGbSi pJ9Os/jf3n127Ww27EStBPa479Y7TtxXZkpVwGrLo1xYjp8DZDv8yGOkk9ymXdjH OPaFyc3RX3l0Azid8UziKuyE1GIRTRqDVrIcsL4yJYESNtVTdXrmj0znz5SxCxE= =ssU3 -----END PGP SIGNATURE----- ------------------------------------------------------------------------------ Try New Relic Now & We'll Send You this Cool Shirt New Relic is the only SaaS-based application performance monitoring service that delivers powerful full stack analytics. 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