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On 24/04/13 06:14, Ian Davis wrote:
> Modularity & hardware often don't go well together.  You refer to
> it as firmware, but it's really fpga configuration bitfiles that
> are needed.
> 
> Bitfiles are all or nothing affairs.   Any change (at all)
> requires fully rebuilding using the fpga-vendor compilation tools.
> It's not like linking software modules together.  The builds are
> all or nothing.
> 

Sure. So this is source modularity, rather than binary modularity.

> If you want to have 4 variants for a given platform, you'll need
> to store 4 bitfiles.  Any common change across varients means
> running through 4 builds in the fpga-vendor tools.   Any additional
> orthogonal features multiply the number of builds.

Yes, care will need to be taken to define what features warrant a
variant image. Otherwise there will be an impractical number of
permutations.

However, developers will only need to care about one variant at once.
So if the Makefiles are designed with this in mind, it will only be
necessary to build full release packages with all permutations when
some kind of release is being made.

A build server would do a good job of this.

> I suspect an easier approach is a bitfile repository.  Someone
> builds & qualifies an image.  They write an ini/xml/whatever
> descriptor file documenting the feature set, applicable devices,
> etc...  The bitfile is validated, then added to the list of
> available images.  End users could then pick & choose.  ie:
> download demon core, or another bitfile compiled by someone else.

We probably wouldn't do this via an free-access online repository,
because we don't want to depend on an internet connection. Also, it is
better for anyone who wants to produce code to come and do it inside
the project, rather than submitting it from the sidelines.

However, I do see what you're saying. There may be an argument for the
user choosing firmwares from a list rather than selecting one based on
capture parameters. Though this *is* what many logic analysers on the
market are doing.

> Many fpga's download through serial rom's which are slow to
> program. Perhaps many/most devices out there support dynamic
> downloads over USB, but the Logic Sniffer doesn't.

Yes I've always felt it's a great shame the OLS had to have that PIC
in it. It would have been so much better if it had a Cypress FX2, or
an FT2232 with a bootstrapping setup. I guess they did it for
compatibility with SUMP.

As you say, doing variants isn't really practical in the OLS.

>> For example in the RockyLogic devices, the vendor has managed to 
>> achieve sampling at 1GHz on a Spartan 3E! I believe they do this
>> by using clever tricks with the 4 clock phases from a PLL, but
>> that can only work if all the other bells and whistles are
>> removed.
>> 
> Interesting.  They must have carefully hand placed capture flops
> near the I/O's.
> 
> If you limited the inputs as speed increased, it wouldn't
> necessarily impact the core logic much.  ie: 16 inputs at 125Mhz, 8
> inputs at 250Mhz, 4 inputs at 500Mhz, or 2 inputs at 1Ghz.   The
> internal datapath would always be the same width then.

Yes it's amazing. I haven't confirmed this, but it seems they even
support the full number of channels at 1GHz. A really amazing job!


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