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- -------- Original Message --------
Subject: Re: Demon Core
Date: Tue, 23 Apr 2013 22:14:10 -0700
From: Ian Davis <[email protected]>
To: Joel Holdsworth <[email protected]>

Hi Joel,

> 
> I'm keen for us to enable something more versatile that can be
> reused again and again across many devices, and something that is
> in the hands of a community, so that the burden to maintain the
> code doesn't fall on a single person.
> 
> I think the sigrok community are well placed to take up that 
> challenge. There are already several guys who have said they'd like
> to contribute. But I don't want to start yet another SUMP derived
> fork, without reaching out to people who've done previous work.
> 
I see no reason why the fpga source code couldn't be maintained like that.


> Do you know if there's another crowd somewhere I should try and
> make contact with?
> 
The people at "http://dangerousprototypes.com"; and
"http://www.gadgetfactory.net"; are the ones who originally speced the
Logic Sniffer board.   I simply took up the fpga reins when it was
drifting a bit.   I'm not really aware of anyone else.


> Yes, so we're hoping to be able to produce modular framework,
> where features can be selected or removed depending on the
> capability of the device.
> 
Modularity & hardware often don't go well together.  You refer to it as
firmware, but it's really fpga configuration bitfiles that are needed.

Bitfiles are all or nothing affairs.   Any change (at all) requires
fully rebuilding using the fpga-vendor compilation tools.  It's not like
linking software modules together.  The builds are all or nothing.

If you want to have 4 variants for a given platform, you'll need to
store 4 bitfiles.  Any common change across varients means running
through 4 builds in the fpga-vendor tools.   Any additional orthogonal
features multiply the number of builds.

I suspect an easier approach is a bitfile repository.  Someone builds &
qualifies an image.  They write an ini/xml/whatever descriptor file
documenting the feature set, applicable devices, etc...  The bitfile is
validated, then added to the list of available images.  End users could
then pick & choose.  ie: download demon core, or another bitfile
compiled by someone else.


> Also the most interesting devices can be bootstrapped at runtime,
> so that you can select from several firmware variants depending on
> what the user wants to do.
> 
Many fpga's download through serial rom's which are slow to program.
Perhaps many/most devices out there support dynamic downloads over USB,
but the Logic Sniffer doesn't.


> For example I can imagine having a very simple firmware that has
> been optimized for ultra high speed sampling, and so it would need
> to be much simplified e.g. have a limited triggering capability. If
> the user wants to sample more slowly we can load a more featureful
> image having compression, and advanced triggers baked into it.
> 
Again, I think your talking a repository of bitfiles.


> For example in the RockyLogic devices, the vendor has managed to 
> achieve sampling at 1GHz on a Spartan 3E! I believe they do this
> by using clever tricks with the 4 clock phases from a PLL, but that
> can only work if all the other bells and whistles are removed.
> 
Interesting.  They must have carefully hand placed capture flops near
the I/O's.

If you limited the inputs as speed increased, it wouldn't necessarily
impact the core logic much.  ie: 16 inputs at 125Mhz, 8 inputs at
250Mhz, 4 inputs at 500Mhz, or 2 inputs at 1Ghz.   The internal datapath
would always be the same width then.


> Yes that would be very helpful. It seems like your knowledge on
> these would be very valuable. If you would like to join in, please
> do drop the #sigrok channel on freenode IRC.
> 
I'll try, but I work startup hours currently.  Basically my life is work
& sleep.   Anything beyond is hit or miss.

Cheers!
- -- Ian



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