Hi, I found other portability issues in the design, they will require modifications to most of the code.
1. reset The design is coded specifically for FPGA, where all FlipFlops power up with in the state zero. I am an ASIC developer so this bothers me. But the main issue is the reset signal for the logic is not connected at all, so there is no way to reset the design except power-up. If we would port the design to a board with a proper reset signal, and we would wish to use it, the RTL would have to be modified, so control logic uses the reset, while the data paths usually can work without reset. Currently many control signals are initialized to zero in the RTL, this is required for the simulation to work properly, but it prevents a proper tesr for the reset signal. The solution is to use a macro for the initialized value (`define INIT = '0) and for the reset test use an undefined value for initialization (`define INIT = 'x). 2. use of nonblocking assignment (=) for FlipFlops The correct assignment operator for FlipFlops is blocking (<=), many modern synthesis tools report errors here. I am not sure if this is an archaic coding style or it is due to conversion from VHDL, but it should be fixed. The problem is, it seems some tests rely it, and it will take me some time to understand why. The execution order in the simulator depends on the used operator, the unit delays (#1) in the combinatorial logic are probably there to force a certain execution order, but they should not be necessary. I also have issues with the coding style for registers, where the combinatorial input into the register is coded separately from the register itself, and the combinatorial logic is using approaches typical for sequential languages. This is very uncommon, but not actually a bug. Regards, Iztok Jeras ------------------------------------------------------------------------------ Introducing AppDynamics Lite, a free troubleshooting tool for Java/.NET Get 100% visibility into your production application - at no cost. Code-level diagnostics for performance bottlenecks with <2% overhead Download for free and get started troubleshooting in minutes. http://p.sf.net/sfu/appdyn_d2d_ap1 _______________________________________________ sigrok-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/sigrok-devel
