Hi Joel,
On Sat, May 25, 2013 at 2:08 PM, Joel Holdsworth
<[email protected]>wrote:
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> Hi Iztok,
>
> A couple of things to discuss with you...
>
> First, I've just been doing a little work on the butterfly logic.
>
> https://github.com/jhol/butterflylogic/commits/public
>
> This branch contains a simple infrastructure to port the project for
> various boards. The user can now do the following:
>
> $ ./configure --board--board=boards/openbench-logic-sniffer/board
> $ make syn
I do not have enough experience with configure to know, how it would help.
For synthesis the only dependency is the vendor tool. Although sometimes an
older version of the tool is required, this is usually, because the parser
became more strict, so the issue can be seen as a bug to be fixed in the
source. Some very old Xilinx devices are not supported in the latest ISE
tools, but we will probably not encounter any. For simulation I will
probably create separate Makefile-s for Icarus and ModelSim, I can use a
single file, if I find a good way to do it. I will probably later add a
code coverage tool, but not an open source one,
Covered<http://covered.sourceforge.net/> does
not support Verilog 2001 well. In any case coverage is less important.
>
>
The board files specify the FPGA and the constraints file. Specifying
> a board is not mandatory. If no board file is specified synthesis will
> be disabled.
>
> The project then has a central project file that lists the sources,
> and the top-level module. From this we can do the synthesis, as well
> as in the future make IDE project files for debugging purposes.
>
I had a quick look at your environment, but I have not attempted to run it
yet, so I have some questions based only on your description. Each
synthesis project, regardless of vendor, requires the definition of the
next information:
- source list, name of the top level module, additional macro defininitions
- FPGA pinout (which pin is connected to which signal
- IO constraints (IO standard type, voltage, current, slew rate, optional
pullup, ...)
- timing constraints (for IO and internal code)
This information is usually in a vendor specific format. In most cases this
files (text or XML or ...) are just committed to VCS. I am under the
impression you are trying to create all this files from tool agnostic files
"a central project file that lists the sources"
(prj/src/logic_sniffer_top.prj), this would be hard and impractical. But I
could have understood incorrectly.
>
> Some things could be improved - e.g. the layout of the project folder,
> but I wanted to submit it sooner rather than later. Also the mapper
> says the current version of the source won't fit in the OLS FPGA - I
> don't know if this is a mistake or not.
>
I was able to finish synthesis with most of my updates to the source, but I
am not sure how many mistakes I made, therefore my current focus on tests.
>
> The branch also contains an automated tidy-up verilog patch, deleting
> trailing whitespace, replacing tabs with spaces, and replacing are the
> CRLFs with LFs.
>
OK, but please do not make it automatic, I do not like if tools update
source file, without user knowledge.
>
> Second, is about licensing. It seems like there's several licenses in
> the code now. Some files are missing copyright headers. It seems like
> there's a mixture of LGPL and GPL 2 and 3. Then I see you added the
> Xilinx headers in the lib/ folder - which seem to be proprietary. Do
> you need these files to be here? because it seems like they shouldn't
> be. Then all the (L)GPL files need to be rationalised to a common license.
>
I added a source file with a GPL 3 license "rtl/cdc.v" this can be changed
to GPL/LGPL 2. LGPL is the preferred license for HDL projects, since they
are similar to libraries. There were many discussions on OpenCores,
regarding licensing, but I think LGPL is a good choice. I actually plan to
license the original version (not the copy in this project) of cdc.v under
CC0 (public domain), since the code is very common and generic. It is
possible I added some test files without a license, you can assume they are
GPL/LGPL. For test files GPL is also appropriate, since this files are
rarely reused elsewhere.
Regarding lib/ folder file, you can remove them right away, I will use the
originals from the Xiling ISE installation path.
> Any thought about all this?
>
> Joel
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