>>> Vendor project files are needed for running the tools in both GUI >>> or batch CLI mode. The GUI can be avoided, the mouse click >>> sequence is usually replace by a TCL script. Almost everything >>> the tool offers can be done without a GUI, but project files are >>> still needed. > >In minsoc I believe these are being generated from a language agnostic >list.
This is one of the things in MinSoC that I didn't like, for those project files are in a propietary format which is bound to change without notice. Most tools (Icarus, Verilator...) allow you to specify verilog source files as command-line arguments, so you can keep your proprietary tool projects down to a minimum. At first, I could not find a way to do the same with Xilinx's synthesizer, but in the end I managed to do it with Verilog's keyword "`uselib" like this: `define OR10 dir=/blah/blah/OpenRISC/OR10 libext=.v `define OR10_CPU dir=/blah/blah/OpenRISC/OR10/CPU libext=.v ... `uselib `OR10 `OR10_CPU ... That way, whenever you reference a module, the synthesizer will try and find it in those directories, so that you do not need to add those paths or files to any vendor-specific project file. Regards, rdiez ------------------------------------------------------------------------------ Get 100% visibility into Java/.NET code with AppDynamics Lite It's a free troubleshooting tool designed for production Get down to code-level detail for bottlenecks, with <2% overhead. Download for free and get started troubleshooting in minutes. http://p.sf.net/sfu/appdyn_d2d_ap2 _______________________________________________ sigrok-devel mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/sigrok-devel
