From: Gwenhael Goavec-Merou <gwenhael.goavec-me...@trabucayre.com> With trigger enabled, and with pulseview, a second (or more) acquisition start immediatly instead of blocking. It's mandatory to try several times to have a correct behavior.
According to http://mygizmos.org/ols/Logic-Sniffer-FPGA-Spec.pdf section 2.3.1 p.8, the openbench logic sniffer must be reset before each arm command. This patch may fix bug #809 Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-me...@trabucayre.com> --- Changes v1 -> v2: * use the new ols_send_reset instead of duplicate the reset sequence (W. Sang). --- src/hardware/openbench-logic-sniffer/api.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/hardware/openbench-logic-sniffer/api.c b/src/hardware/openbench-logic-sniffer/api.c index c045953..5e74a52 100644 --- a/src/hardware/openbench-logic-sniffer/api.c +++ b/src/hardware/openbench-logic-sniffer/api.c @@ -473,6 +473,14 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi) return SR_ERR; } if (devc->num_stages > 0) { + /* + * According to http://mygizmos.org/ols/Logic-Sniffer-FPGA-Spec.pdf + * reset command must be send prior each arm command + */ + sr_dbg("Send reset command before trigger configure"); + if (ols_send_reset(serial) != SR_OK) + return SR_ERR; + delaycount = readcount * (1 - devc->capture_ratio / 100.0); devc->trigger_at = (readcount - delaycount) * 4 - devc->num_stages; for (i = 0; i <= devc->num_stages; i++) { -- 2.10.2 ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot _______________________________________________ sigrok-devel mailing list sigrok-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/sigrok-devel
