I'm using Pulseview and an 8-bit logic analyser to debug an SPI exchange. The
protocol lacks a Chip Select signal; instead there is a CM1 signal that toggles
at each byte.
The SPI decoder with CS# disabled works for some acquisitions I make, but others
are incorrect because the decoder is out of sync. I can get the correct value
for one byte out of two by synchronizing on CM1 low or high. I can see all the
bytes by using two SPI decoders, but that's not ideal.
There would be a number of ways to modify the SPI decoder to solve my problem:
1) ignore the first 1 to 7 bits acquired according to CLK transitions, with "-1"
to "-8" added to the "CS#" menu in addition to the existing "-"
2) reset byte acquisition when the designated CLK is steady for a specified
amount of time or sample. 1us to 20 ms, or 6 to 100000 acquisition periods would
do for me.
3) reset byte acquisition on edge of the designated CS#, in a new "edge" setting
of "CS# polarity" beside the existing "active-low" and "active-high"
I figure how to modify the decoder to add menu items and extract their setting,
but so far I'm lost on the decoder itsef. Any hint appreciated.
I have put a sample trace at http://fgrieu.free.fr/licstartup.zip (56 KB,
containing licstartup.sr and licstartup.pvs)
The bottom has three SPI decoders, synchronizing on CM1 active low, active high,
and disabled.
If we look starting at +497673833ns, the data on MOSI really is 05 03 01 00 35
64 05 03 00 00 ED 7D.
SPILO shows the bytes sent with CM1 low, SPIHI with CM1 hi, and SPI has all data
but is out of sync.
Francois Grieu
_______________________________________________
sigrok-devel mailing list
sigrok-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/sigrok-devel
