Hi Stephen,
In your previous email, you said:
> In general, the code we distribute in Flexus releases is suitable for
> simulating ordinary systems. However, different groups at CMU are
> involved in architecture research, and the code/components associated with
> this research is not typically included in the release distribution. For
> example, in Temporal Streaming and Spatial Memory Streaming, we fetch
> blocks into a node's local cache hierarchy through PrefetchReq's. We have
> not included the component that actually sits within the hierarchy (e.g.,
> between L1d and L2) and issues prefetches, but we do include the necessary
> support from the Caches.
From what you said, I understand that if I want to implement a
component that generates PrefetchReq's, I can trust/count on the Cache
component to deal with that particular message as explained in
MemoryMessage.hpp. Is that right?
Is there anything specific that you think I should know with respect to
the Cache component implementation when it comes to how it treats the
PrefetchRequest messages?
Thank you for your time.
Ioana
From mrinal at ece.umn.edu Tue Oct 3 19:49:56 2006
From: mrinal at ece.umn.edu (Mrinal Nath)
List-Post: [email protected]
Date: Tue Oct 3 19:50:38 2006
Subject: [Simflex] Piranha Dir states
Message-ID: <[email protected]>
Hi,
Can someone please provide some details about what the PiranhaDirStates
mean.
I can understand the stable states of D_M, D_O, D_S, D_I.
I think I also understand some of the other states like D_S2MW (I think
this means, "going from S to M state due to a write")
But I cannot guess out what most the other states mean. Some help will
be very useful, and will also serve as documentation about those states.
Thanks
- Mrinal
From twenisch at ece.cmu.edu Wed Oct 4 00:52:21 2006
From: twenisch at ece.cmu.edu (Thomas Wenisch)
List-Post: [email protected]
Date: Wed Oct 4 00:52:25 2006
Subject: [Simflex] What types of memory messages are used in CMPFlex?
In-Reply-To: <[email protected]>
References: <[email protected]>
<pine.lnx.4.53l-ece.cmu.edu.0609291402200.16...@aprile.ece.cmu.edu>
<[email protected]>
Message-ID: <[email protected]>
Hi Ioana,
On Tue, 3 Oct 2006, Ioana Burcea wrote:
> Hi Stephen,
>
> In your previous email, you said:
>
>
>> In general, the code we distribute in Flexus releases is suitable for
>> simulating ordinary systems. However, different groups at CMU are
>> involved in architecture research, and the code/components associated with
>> this research is not typically included in the release distribution. For
>> example, in Temporal Streaming and Spatial Memory Streaming, we fetch
>> blocks into a node's local cache hierarchy through PrefetchReq's. We have
>> not included the component that actually sits within the hierarchy (e.g.,
>> between L1d and L2) and issues prefetches, but we do include the necessary
>> support from the Caches.
>
> From what you said, I understand that if I want to implement a component that
> generates PrefetchReq's, I can trust/count on the Cache component to deal
> with that particular message as explained in MemoryMessage.hpp. Is that
> right?
Yes, all of the Flexus memory components/caches should correctly handle
*Prefetch* messages. Be sure you look at the comments in
MemoryMessage.hpp to see the intended semantics of each message. Note
that the caches have both FrontSideIn_Request and FrontSideIn_Prefetch
ports - Prefetch messages should be handled at either, but are intended to
be sent on the _Prefetch ports (the _Request ports have priority when
there is a backlog of requests).
Let us know if you have questions about specific messages.
Regards,
-Tom Wenisch
>
> Is there anything specific that you think I should know with respect to the
> Cache component implementation when it comes to how it treats the
> PrefetchRequest messages?
>
> Thank you for your time.
> Ioana
> _______________________________________________
> SimFlex mailing list
> [email protected]
> https://sos.ece.cmu.edu/mailman/listinfo/simflex
> SimFlex web page: http://www.ece.cmu.edu/~simflex
>
From jsmolens+ at ece.cmu.edu Wed Oct 4 10:57:51 2006
From: jsmolens+ at ece.cmu.edu (Jared C. Smolens)
List-Post: [email protected]
Date: Wed Oct 4 10:57:54 2006
Subject: [Simflex] Piranha Dir states
Message-ID: <[email protected]>
Hi Mrinal,
I have posted the Flexus CMP Cache Coherence state diagram on the SimFlex
webpage (click on Software). States such as D_S2MW are transient states.
You have the correct interpretation for D_S2MW.
Jared
Excerpts From Mrinal Nath <[email protected]>:
[Simflex] Piranha Dir states: Mrinal Nath <[email protected]>
>Can someone please provide some details about what the PiranhaDirStates
>mean.
>
>I can understand the stable states of D_M, D_O, D_S, D_I.
>I think I also understand some of the other states like D_S2MW (I think
>this means, "going from S to M state due to a write")
>
>But I cannot guess out what most the other states mean. Some help will
>be very useful, and will also serve as documentation about those states.
Jared Smolens ----------- Electrical and Computer Engineering
www.rabidpenguin.org ------------- Carnegie Mellon University
jsmolens AT ece.cmu.edu ------ HH A-313 ------ Pittsburgh, PA
