Hi,
I have two questions:
1. I just want to check that evict messages (due to invalidation or
replacement) are always sent through the snoop channel. This is my
impression by looking at the code.
2. What happens when a port is not wired? What happens with the messages
that would have been sent through that port, etc?
Thank you,
Ioana
From twenisch at ece.cmu.edu Wed Oct 4 12:46:01 2006
From: twenisch at ece.cmu.edu (Thomas Wenisch)
List-Post: [email protected]
Date: Wed Oct 4 12:46:06 2006
Subject: [Simflex] evict messages & not wired ports
In-Reply-To: <[email protected]>
References: <[email protected]>
Message-ID: <[email protected]>
Hi Ioanna,
On Wed, 4 Oct 2006, Ioana Burcea wrote:
> Hi,
>
> I have two questions:
>
> 1. I just want to check that evict messages (due to invalidation or
> replacement) are always sent through the snoop channel. This is my impression
> by looking at the code.
Yes, all messages that potentially carry data from the CPU towards memory
travel in the Snoop channel (the ordered delivery of the snoop channel
assures that consistency and coherence for these values are maintained).
> 2. What happens when a port is not wired? What happens with the messages that
> would have been sent through that port, etc?
They are silently dropped. (I.e., the function that is called when the
message is "sent" returns without effect.)
Regards,
-Tom Wenisch
Computer Architecture Lab
Carnegie Mellon University
From ioana at eecg.toronto.edu Wed Oct 4 14:22:19 2006
From: ioana at eecg.toronto.edu (Ioana Burcea)
List-Post: [email protected]
Date: Wed Oct 4 14:22:35 2006
Subject: [Simflex] isQuiesced & drive order
Message-ID: <[email protected]>
Hi,
Two questions again :)
1. What is isQuiesced() used for (what are the semantics for the return
value)?
2. Could you please explain why the drive order in UniFlex.OoO specifies
the memory (MemoryLoopback) first and then L2 cache?
Thanks,
Ioana
From twenisch at ece.cmu.edu Wed Oct 4 22:14:44 2006
From: twenisch at ece.cmu.edu (Thomas Wenisch)
List-Post: [email protected]
Date: Wed Oct 4 22:14:50 2006
Subject: [Simflex] isQuiesced & drive order
In-Reply-To: <[email protected]>
References: <[email protected]>
Message-ID: <[email protected]>
Hi Ioana,
On Wed, 4 Oct 2006, Ioana Burcea wrote:
> Hi,
>
> Two questions again :)
>
> 1. What is isQuiesced() used for (what are the semantics for the return
> value)?
isQuiesced() is part of Flexus' flexpoint support. In order to
simplify the code in saveState() and loadState(), Flexus only saves
non-transient state in flexpoints. Prior to saving a flexpoint the
simulation is "quiesced", which means that all in flight operations,
memory transactions, etc, are brought to a halt.
When you tell Flexus to save its state, Flexus sets a global flag
indicating that it is trying to quiesce. This causes certain components
(e.g., the InorderSimicsFeeder) to stop injecting new
instructions/transactions into the system. Then, the simulation
continues, and, every cycle, Flexus calls isQuiesced() on every component.
If a component has no transient state (all queues are empty, no in-flight
transactions, etc.) it returns true. When all components simulataneously
return true, Flexus calls saveState() on every component to write out a
flexpoint.
So, to implement this function, each component should return "false" if it
has in-flight transactions and is not ready to save, and "true" if it is
prepared to save its current state in its saveState() function.
Nowadays, these functions aren't so important anymore, because we use
TraceFlex to generate flexpoints, and there is no transient state in
TraceFlex (hence, isQuiesced() is always true for all trace components).
In principle, the OoO simulator should be able to write out flexpoints as
well, but I haven't tested this in a long time, so it may not be working.
The inorder timing simulators can definately write flexpoints, and
isQuiesced() is critical to that process.
>
> 2. Could you please explain why the drive order in UniFlex.OoO specifies the
> memory (MemoryLoopback) first and then L2 cache?
>
I believe this shaves a cycle off the time it takes memory replies to
get to the CPU. Assuming you set the main memory latency to
something normal, this doesn't matter. If for some reason you set
memory latency to 1 cycle (to get a simulation to advance quickly), this
ordering accelerates memory replies.
Regards,
-Tom Wenisch
Computer Architecture Lab
Carnegie Mellon University
From mrinal at ece.umn.edu Thu Oct 5 02:27:53 2006
From: mrinal at ece.umn.edu (Mrinal Nath)
List-Post: [email protected]
Date: Thu Oct 5 02:28:05 2006
Subject: [Simflex] Piranha Dir states
In-Reply-To: <[email protected]>
References: <[email protected]>
Message-ID: <[email protected]>
Hi Jared,
Thanks a lot for posting the state diagram.
However, by going though the code, I noticed that the main memory
replies to a read request (which missed in L1 and L2) by returning a
"MissReplyWritable" message. And the directory keeps this line in the M
state, with the owner set to the requesting L1. (correct me if I am wrong)
So, if I am correct above, then in this particular example the state
diagram document is not consistent with the code. i.e. the document (on
pg 2) shows a transition from I to S (transition labeled 1) but
according to the code, the transition seems to be from I to M.
Please let me know if I am on the right track, or I am missing something.
Also, I when the memory replies to L2 for a miss, I would like to
allocate the block in the L2 and then pass it on to L1 (currently the
block is allocated only in L1). Can this be done? How? Is there any
inherent drawback/problem in allocating the line in L2 ?
Thanks
- Mrinal
Jared C. Smolens wrote:
> Hi Mrinal,
>
> I have posted the Flexus CMP Cache Coherence state diagram on the SimFlex
> webpage (click on Software). States such as D_S2MW are transient states.
> You have the correct interpretation for D_S2MW.
>
> Jared
>
> Excerpts From Mrinal Nath <[email protected]>:
> [Simflex] Piranha Dir states: Mrinal Nath <[email protected]>
>
>>Can someone please provide some details about what the PiranhaDirStates
>>mean.
>>
>>I can understand the stable states of D_M, D_O, D_S, D_I.
>>I think I also understand some of the other states like D_S2MW (I think
>>this means, "going from S to M state due to a write")
>>
>>But I cannot guess out what most the other states mean. Some help will
>>be very useful, and will also serve as documentation about those states.
>
>
>
>
> Jared Smolens ----------- Electrical and Computer Engineering
> www.rabidpenguin.org ------------- Carnegie Mellon University
> jsmolens AT ece.cmu.edu ------ HH A-313 ------ Pittsburgh, PA
>
> _______________________________________________
> SimFlex mailing list
> [email protected]
> https://sos.ece.cmu.edu/mailman/listinfo/simflex
> SimFlex web page: http://www.ece.cmu.edu/~simflex
From jsmolens+ at ece.cmu.edu Thu Oct 5 11:43:48 2006
From: jsmolens+ at ece.cmu.edu (Jared C. Smolens)
List-Post: [email protected]
Date: Thu Oct 5 11:43:53 2006
Subject: [Simflex] Piranha Dir states
Message-ID: <[email protected]>
Hi Mrinal,
See inline...
Excerpts From Mrinal Nath <[email protected]>:
Re: [Simflex] Piranha Dir states: Mrinal Nath <[email protected]>
>Hi Jared,
>Thanks a lot for posting the state diagram.
>
>However, by going though the code, I noticed that the main memory
>replies to a read request (which missed in L1 and L2) by returning a
>"MissReplyWritable" message. And the directory keeps this line in the M
>state, with the owner set to the requesting L1. (correct me if I am
wrong)
Yes, this is the behavior that should be happening.
>So, if I am correct above, then in this particular example the state
>diagram document is not consistent with the code. i.e. the document (on
>pg 2) shows a transition from I to S (transition labeled 1) but
>according to the code, the transition seems to be from I to M.
>
>Please let me know if I am on the right track, or I am missing
something.
You're right. It looks like the external requests diagram is missing a
transition from GetS to M, upon receiving a writable external miss reply.
There's also a transition from S to GetM that's missing. I have updated
the diagram.
>Also, I when the memory replies to L2 for a miss, I would like to
>allocate the block in the L2 and then pass it on to L1 (currently the
>block is allocated only in L1). Can this be done? How? Is there any
>inherent drawback/problem in allocating the line in L2 ?
This can be done by setting up an eviction when the miss reply is
received (handle_D_ExtGet() is probably the best place) and making sure
the state/ownership bits are set properly. If the L2 size is similar to
the aggregate L1 size, then you may be wasting cache space by replicating
blocks. If the L2 is big, this will not matter so much.
Also, be aware that Piranha is non-inclusive, so blocks allocated in an
L1 *may* be in the L2, but that is not guaranteed (the L2 can replace a
block without telling L1's who may also have a copy). If you require
inclusion, you'll have to do a lot of pen-and-paper work to make sure you
can guarantee that.
Cheers,
Jared
>Thanks
>- Mrinal
>
>Jared C. Smolens wrote:
>> Hi Mrinal,
>>
>> I have posted the Flexus CMP Cache Coherence state diagram on the
SimFlex
>> webpage (click on Software). States such as D_S2MW are transient
states.
>> You have the correct interpretation for D_S2MW.
>>
>> Jared
>>
>> Excerpts From Mrinal Nath <[email protected]>:
>> [Simflex] Piranha Dir states: Mrinal Nath <[email protected]>
>>
>>>Can someone please provide some details about what the
PiranhaDirStates
>>>mean.
>>>
>>>I can understand the stable states of D_M, D_O, D_S, D_I.
>>>I think I also understand some of the other states like D_S2MW (I
think
>>>this means, "going from S to M state due to a write")
>>>
>>>But I cannot guess out what most the other states mean. Some help will
>>>be very useful, and will also serve as documentation about those
states.
>>
>>
>>
>>
>> Jared Smolens ----------- Electrical and Computer Engineering
>> www.rabidpenguin.org ------------- Carnegie Mellon University
>> jsmolens AT ece.cmu.edu ------ HH A-313 ------ Pittsburgh, PA
>>
>> _______________________________________________
>> SimFlex mailing list
>> [email protected]
>> https://sos.ece.cmu.edu/mailman/listinfo/simflex
>> SimFlex web page: http://www.ece.cmu.edu/~simflex
>_______________________________________________
>SimFlex mailing list
>[email protected]
>https://sos.ece.cmu.edu/mailman/listinfo/simflex
>SimFlex web page: http://www.ece.cmu.edu/~simflex
Jared Smolens ----------- Electrical and Computer Engineering
www.rabidpenguin.org ------------- Carnegie Mellon University
jsmolens AT ece.cmu.edu ------ HH A-313 ------ Pittsburgh, PA
