Hi Abu,
TraceFlex is quite fast - it simulates at several MIPS on modern host
machines, and is within a factor of 10-100 of Simics running by itself.
More than 2 hours of simulated time would have passed in several days of
simulation, and the test app should only require seconds of simulated time
to complete.
There is nothing obviously amiss in the debug output you attached - the
warnings regarding unconnected ports are normal for the TraceFlex
simulator.
I suspect that the test application is either completing, and TraceFlex is
failing to detect it, or there is a problem that is causing the test
program to fail to run (i.e., it is crashing, or it didn't like its
command line parameters, or something). Hence, in your multi-day
simulation, you were actually simulating an idle system at the shell
prompt.
I suggest you try to load the simics checkpoint that is created by
"prepare-test-app" without flexus. (Launch simics, and then use the
"read-configuration" command to load the checkpoint; see the Simics User's
Guide for more information on checkpoints in general and
read-configuration in particular). Then, run from this point and inspect
the Simics console to see if the test application is actually running to
completion or is failing.
Regards,
-Tom Wenisch
Computer Architecture Lab
Carnegie Mellon University
On Wed, 30 May 2007, Abu Saad Papa wrote:
> Hi
> I had posted this request earliar but no reply
>> Thank You for the reply. I would like to mention one more thing about the
>> test application. I changed the number of processors to 8 and also the
>> threads to 8. And then tried to run it with TraceCMPFlex and CMPFlex.OoO,
>> the application is running for the past six days and is still running as I
>> am writing this post. Does the application take so much time to execute
>> for a 8-processor CMP? If anyone has tried the test application for
>> 8-processor CMP please inform me how long it takes to execute the
>> application.
>
> I would like to repeat my question again. I was following the flexus
> starting guide and running the test application for multiprocessor
> (DSMFlex or CMPFlex). I had changed the number of processors to 8 and the
> number of threads to 8 as said in the guide. The first step namely
> executing ./prepare-test-app had no problems. But when running the second
> step namely ./create-initial-flexpoint TraceFlex (or
> ./create-initial-flexpoint TraceCMPFlex for CMPFlex.OoO) the simulator is
> running for days. I think I am missing out something very simple. So if
> anyone can help me out in this it will be really nice. I am also
> attaching the debug.out file for your info
>
> 1 <startup.cpp:109> {0}- Initializing Flexus.
> 2 <ComponentManager.cpp:81> {0}- Instantiating system with a width factor
> of: 8
> 3 <SimicsTracer.cpp:555> {0}- Initializing SimicsTracerManager.
> 4 <SimicsTracer.cpp:662> {0}- Connecting: cpu0
> 5 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu0 to
> Simics object cpu0
> 6 <SimicsTracer.cpp:662> {0}- Connecting: cpu1
> 7 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu1 to
> Simics object cpu1
> 8 <SimicsTracer.cpp:662> {0}- Connecting: cpu2
> 9 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu2 to
> Simics object cpu2
> 10 <SimicsTracer.cpp:662> {0}- Connecting: cpu3
> 11 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu3 to
> Simics object cpu3
> 12 <SimicsTracer.cpp:662> {0}- Connecting: cpu4
> 13 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu4 to
> Simics object cpu4
> 14 <SimicsTracer.cpp:662> {0}- Connecting: cpu5
> 15 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu5 to
> Simics object cpu5
> 16 <SimicsTracer.cpp:662> {0}- Connecting: cpu6
> 17 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu6 to
> Simics object cpu6
> 18 <SimicsTracer.cpp:662> {0}- Connecting: cpu7
> 19 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu7 to
> Simics object cpu7
> 20 <SimicsTracer.cpp:684> {0}- Creating DMA map object
> 21 <SimicsTracer.cpp:726> {0}- Connecting to DMA memory map
> 22 <SimicsTracer.cpp:567> {0}- Done initializing SimicsTracerManager.
> 23 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
> 24 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
> 25 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
> 26 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
> 27 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
> 28 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
> 29 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
> 30 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
> 31 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
> 32 <FastCache.hpp:69> {0}- L1d port Reads is not wired
> 33 <FastCache.hpp:69> {0}- L1d port Writes is not wired
> 34 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
> 35 <FastCache.hpp:69> {0}- L1d port Reads is not wired
> 36 <FastCache.hpp:69> {0}- L1d port Writes is not wired
> 37 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
> 38 <FastCache.hpp:69> {0}- L1d port Reads is not wired
> 39 <FastCache.hpp:69> {0}- L1d port Writes is not wired
> 40 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
> 41 <FastCache.hpp:69> {0}- L1d port Reads is not wired
> 42 <FastCache.hpp:69> {0}- L1d port Writes is not wired
> 43 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
> 44 <FastCache.hpp:69> {0}- L1d port Reads is not wired
> 45 <FastCache.hpp:69> {0}- L1d port Writes is not wired
> 46 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
> 47 <FastCache.hpp:69> {0}- L1d port Reads is not wired
> 48 <FastCache.hpp:69> {0}- L1d port Writes is not wired
> 49 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
> 50 <FastCache.hpp:69> {0}- L1d port Reads is not wired
> 51 <FastCache.hpp:69> {0}- L1d port Writes is not wired
> 52 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
> 53 <FastCache.hpp:69> {0}- L1d port Reads is not wired
> 54 <FastCache.hpp:69> {0}- L1d port Writes is not wired
> 55 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
> 56 <FastCache.hpp:69> {0}- L1i port Reads is not wired
> 57 <FastCache.hpp:69> {0}- L1i port Writes is not wired
> 58 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
> 59 <FastCache.hpp:69> {0}- L1i port Reads is not wired
> 60 <FastCache.hpp:69> {0}- L1i port Writes is not wired
> 61 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
> 62 <FastCache.hpp:69> {0}- L1i port Reads is not wired
> 63 <FastCache.hpp:69> {0}- L1i port Writes is not wired
> 64 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
> 65 <FastCache.hpp:69> {0}- L1i port Reads is not wired
> 66 <FastCache.hpp:69> {0}- L1i port Writes is not wired
> 67 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
> 68 <FastCache.hpp:69> {0}- L1i port Reads is not wired
> 69 <FastCache.hpp:69> {0}- L1i port Writes is not wired
> 70 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
> 71 <FastCache.hpp:69> {0}- L1i port Reads is not wired
> 72 <FastCache.hpp:69> {0}- L1i port Writes is not wired
> 73 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
> 74 <FastCache.hpp:69> {0}- L1i port Reads is not wired
> 75 <FastCache.hpp:69> {0}- L1i port Writes is not wired
> 76 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
> 77 <FastCache.hpp:69> {0}- L1i port Reads is not wired
> 78 <FastCache.hpp:69> {0}- L1i port Writes is not wired
> 79 <FastCache.hpp:69> {0}- L2 port Reads is not wired
> 80 <FastCache.hpp:69> {0}- L2 port Writes is not wired
> 81 <FastCache.hpp:69> {0}- L2 port Reads is not wired
> 82 <FastCache.hpp:69> {0}- L2 port Writes is not wired
> 83 <FastCache.hpp:69> {0}- L2 port Reads is not wired
> 84 <FastCache.hpp:69> {0}- L2 port Writes is not wired
> 85 <FastCache.hpp:69> {0}- L2 port Reads is not wired
> 86 <FastCache.hpp:69> {0}- L2 port Writes is not wired
> 87 <FastCache.hpp:69> {0}- L2 port Reads is not wired
> 88 <FastCache.hpp:69> {0}- L2 port Writes is not wired
> 89 <FastCache.hpp:69> {0}- L2 port Reads is not wired
> 90 <FastCache.hpp:69> {0}- L2 port Writes is not wired
> 91 <FastCache.hpp:69> {0}- L2 port Reads is not wired
> 92 <FastCache.hpp:69> {0}- L2 port Writes is not wired
> 93 <FastCache.hpp:69> {0}- L2 port Reads is not wired
> 94 <FastCache.hpp:69> {0}- L2 port Writes is not wired
> 95 <FastBus.hpp:73> {0}- bus port Writes is not wired
> 96 <FastBus.hpp:73> {0}- bus port Reads is not wired
> 97 <FastBus.hpp:73> {0}- bus port Evictions is not wired
> 98 <FastBus.hpp:73> {0}- bus port Flushes is not wired
> 99 <FastBus.hpp:73> {0}- bus port Invalidations is not wired
> 100 <wiring.cpp:79> {0}- initializing Parameters...
> 101 <flexus.cpp:369> {0}- Set stat interval to : 10000000
> 102 <flexus.cpp:389> {0}- Set profile interval to : 10000000
> 103 <flexus.cpp:394> {0}- Set timestamp interval to : 1000000
> 104 <ComponentManager.cpp:96> {0}- Initalizing components...
> 105 <SimicsTracer.cpp:602> {0}- >>>>> OK
> 106 <SimicsTracer.cpp:602> {0}- >>>>> OK
> 107 <SimicsTracer.cpp:602> {0}- >>>>> OK
> 108 <SimicsTracer.cpp:602> {0}- >>>>> OK
> 109 <SimicsTracer.cpp:602> {0}- >>>>> OK
> 110 <SimicsTracer.cpp:602> {0}- >>>>> OK
> 111 <SimicsTracer.cpp:602> {0}- >>>>> OK
> 112 <SimicsTracer.cpp:602> {0}- >>>>> OK
> 113 <flexus.cpp:262> {0}- Timestamp: 2007-May-30 12:36:08
> 114 <FastCacheImpl.cpp:123> {0}- Running with MT width 1
> 115 <flexus.cpp:262> {1000000}- Timestamp: 2007-May-30 12:36:30
> 116 <flexus.cpp:262> {2000000}- Timestamp: 2007-May-30 12:36:53
> 117 <flexus.cpp:262> {3000000}- Timestamp: 2007-May-30 12:37:16
> 118 <flexus.cpp:262> {4000000}- Timestamp: 2007-May-30 12:37:39
> 119 <flexus.cpp:262> {5000000}- Timestamp: 2007-May-30 12:38:02
> 120 <flexus.cpp:262> {6000000}- Timestamp: 2007-May-30 12:38:25
> 121 <flexus.cpp:262> {7000000}- Timestamp: 2007-May-30 12:38:47
> 122 <flexus.cpp:262> {8000000}- Timestamp: 2007-May-30 12:39:10
> 123 <flexus.cpp:262> {9000000}- Timestamp: 2007-May-30 12:39:33
> 124 <flexus.cpp:262> {10000000}- Timestamp: 2007-May-30 12:39:55
> 125 <flexus.cpp:273> {10000000}- Saving stats at: 10000000
> 126 <flexus.cpp:292> {10000000}- Writing profile at: 10000000
> 127 <flexus.cpp:262> {11000000}- Timestamp: 2007-May-30 12:40:18
> 128 <flexus.cpp:262> {12000000}- Timestamp: 2007-May-30 12:40:41
> 129 <flexus.cpp:262> {13000000}- Timestamp: 2007-May-30 12:41:03
> 130 <flexus.cpp:262> {14000000}- Timestamp: 2007-May-30 12:41:27
> 131 <flexus.cpp:262> {15000000}- Timestamp: 2007-May-30 12:41:50
> 132 <flexus.cpp:262> {16000000}- Timestamp: 2007-May-30 12:42:13
> 133 <flexus.cpp:262> {17000000}- Timestamp: 2007-May-30 12:42:36
> 134 <flexus.cpp:262> {18000000}- Timestamp: 2007-May-30 12:42:59
> 135 <flexus.cpp:262> {19000000}- Timestamp: 2007-May-30 12:43:21
> 136 <flexus.cpp:262> {20000000}- Timestamp: 2007-May-30 12:43:44
> 137 <flexus.cpp:273> {20000000}- Saving stats at: 20000000
> 138 <flexus.cpp:292> {20000000}- Writing profile at: 20000000
> 139 <flexus.cpp:262> {21000000}- Timestamp: 2007-May-30 12:44:07
> 140 <flexus.cpp:262> {22000000}- Timestamp: 2007-May-30 12:44:29
> 141 <flexus.cpp:262> {23000000}- Timestamp: 2007-May-30 12:44:52
> 142 <flexus.cpp:262> {24000000}- Timestamp: 2007-May-30 12:45:15
> 143 <flexus.cpp:262> {25000000}- Timestamp: 2007-May-30 12:45:37
> 144 <flexus.cpp:262> {26000000}- Timestamp: 2007-May-30 12:46:00
> 145 <flexus.cpp:262> {27000000}- Timestamp: 2007-May-30 12:46:23
> 146 <flexus.cpp:262> {28000000}- Timestamp: 2007-May-30 12:46:46
> 147 <flexus.cpp:262> {29000000}- Timestamp: 2007-May-30 12:47:09
> 148 <flexus.cpp:262> {30000000}- Timestamp: 2007-May-30 12:47:32
> 149 <flexus.cpp:273> {30000000}- Saving stats at: 30000000
> 150 <flexus.cpp:292> {30000000}- Writing profile at: 30000000
> 151 <flexus.cpp:262> {31000000}- Timestamp: 2007-May-30 12:47:56
> 152 <flexus.cpp:262> {32000000}- Timestamp: 2007-May-30 12:48:19
> 153 <flexus.cpp:262> {33000000}- Timestamp: 2007-May-30 12:48:42
> 154 <flexus.cpp:262> {34000000}- Timestamp: 2007-May-30 12:49:05
> 155 <flexus.cpp:262> {35000000}- Timestamp: 2007-May-30 12:49:28
> 156 <flexus.cpp:262> {36000000}- Timestamp: 2007-May-30 12:51:54
> 157 <flexus.cpp:262> {37000000}- Timestamp: 2007-May-30 12:52:17
> 158 <flexus.cpp:262> {38000000}- Timestamp: 2007-May-30 12:52:40
> 159 <flexus.cpp:262> {39000000}- Timestamp: 2007-May-30 12:53:03
> 160 <flexus.cpp:262> {40000000}- Timestamp: 2007-May-30 12:53:24
> 161 <flexus.cpp:273> {40000000}- Saving stats at: 40000000
> 162 <flexus.cpp:292> {40000000}- Writing profile at: 40000000
> 163 <flexus.cpp:262> {41000000}- Timestamp: 2007-May-30 12:53:46
> 164 <flexus.cpp:262> {42000000}- Timestamp: 2007-May-30 12:54:09
> 165 <flexus.cpp:262> {43000000}- Timestamp: 2007-May-30 12:54:32
> 166 <flexus.cpp:262> {44000000}- Timestamp: 2007-May-30 12:54:54
> 167 <flexus.cpp:262> {45000000}- Timestamp: 2007-May-30 12:55:17
> 168 <flexus.cpp:262> {46000000}- Timestamp: 2007-May-30 12:55:39
> 169 <flexus.cpp:262> {47000000}- Timestamp: 2007-May-30 12:56:01
> 170 <flexus.cpp:262> {48000000}- Timestamp: 2007-May-30 12:56:23
> 171 <flexus.cpp:262> {49000000}- Timestamp: 2007-May-30 12:56:46
> 172 <flexus.cpp:262> {50000000}- Timestamp: 2007-May-30 12:57:08
> 173 <flexus.cpp:273> {50000000}- Saving stats at: 50000000
> 174 <flexus.cpp:292> {50000000}- Writing profile at: 50000000
> 175 <flexus.cpp:262> {51000000}- Timestamp: 2007-May-30 12:57:31
> 176 <flexus.cpp:262> {52000000}- Timestamp: 2007-May-30 12:57:53
> 177 <flexus.cpp:262> {53000000}- Timestamp: 2007-May-30 12:58:16
> 178 <flexus.cpp:262> {54000000}- Timestamp: 2007-May-30 12:58:38
> 179 <flexus.cpp:262> {55000000}- Timestamp: 2007-May-30 12:59:00
>
> I ended the simulation here as previously it was running for six days
> without fininshing. Thanks in advance.
>
>
> Abu Saad Papa
> http://research.iiit.net/~abu_saad/
> M.S VLSI
> IIIT, Hyderabad.
>
> "GOD GIVES MAN GETS ........
> GOD FORGIVES MAN FORGETS...."
> _______________________________________________
> SimFlex mailing list
> [email protected]
> https://sos.ece.cmu.edu/mailman/listinfo/simflex
> SimFlex web page: http://www.ece.cmu.edu/~simflex
>
From abu_saad at research.iiit.net Sat Jun 2 01:02:11 2007
From: abu_saad at research.iiit.net (Abu Saad Papa)
List-Post: [email protected]
Date: Sat Jun 2 01:03:13 2007
Subject: [Simflex] Difference between DSMFLex and CMPFlex
In-Reply-To: <[email protected]>
References: <[email protected]>
<[email protected]>
<[email protected]>
<[email protected]>
<[email protected]>
Message-ID: <[email protected]>
Hi Tom
Thank you for the suggestion, I think the flexus application is failing
as I tried what you said i.e load the simics checkpoint that is created
by "prepare-test-app" without flexus and got the following error
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
[Turbo] Trampoline found at block start.
Assertion failed: pthread_create(&thread_array[i], NULL, filter,
&thread_ids[i]) == 0, file filter.c, line 200
Abort - core dumped
I don't have any idea what this problem is. Hope I will get some valuable
inputs.
Regards,
Abu Saad
> Hi Abu,
>
> TraceFlex is quite fast - it simulates at several MIPS on modern host
> machines, and is within a factor of 10-100 of Simics running by itself.
> More than 2 hours of simulated time would have passed in several days of
> simulation, and the test app should only require seconds of simulated time
> to complete.
>
> There is nothing obviously amiss in the debug output you attached - the
> warnings regarding unconnected ports are normal for the TraceFlex
> simulator.
>
> I suspect that the test application is either completing, and TraceFlex is
> failing to detect it, or there is a problem that is causing the test
> program to fail to run (i.e., it is crashing, or it didn't like its
> command line parameters, or something). Hence, in your multi-day
> simulation, you were actually simulating an idle system at the shell
> prompt.
>
> I suggest you try to load the simics checkpoint that is created by
> "prepare-test-app" without flexus. (Launch simics, and then use the
> "read-configuration" command to load the checkpoint; see the Simics User's
> Guide for more information on checkpoints in general and
> read-configuration in particular). Then, run from this point and inspect
> the Simics console to see if the test application is actually running to
> completion or is failing.
>
> Regards,
> -Tom Wenisch
> Computer Architecture Lab
> Carnegie Mellon University
>
> On Wed, 30 May 2007, Abu Saad Papa wrote:
>
>> Hi
>> I had posted this request earliar but no reply
>>> Thank You for the reply. I would like to mention one more thing about
>>> the
>>> test application. I changed the number of processors to 8 and also the
>>> threads to 8. And then tried to run it with TraceCMPFlex and
>>> CMPFlex.OoO,
>>> the application is running for the past six days and is still running
>>> as I
>>> am writing this post. Does the application take so much time to execute
>>> for a 8-processor CMP? If anyone has tried the test application for
>>> 8-processor CMP please inform me how long it takes to execute the
>>> application.
>>
>> I would like to repeat my question again. I was following the flexus
>> starting guide and running the test application for multiprocessor
>> (DSMFlex or CMPFlex). I had changed the number of processors to 8 and
>> the
>> number of threads to 8 as said in the guide. The first step namely
>> executing ./prepare-test-app had no problems. But when running the
>> second
>> step namely ./create-initial-flexpoint TraceFlex (or
>> ./create-initial-flexpoint TraceCMPFlex for CMPFlex.OoO) the simulator
>> is
>> running for days. I think I am missing out something very simple. So if
>> anyone can help me out in this it will be really nice. I am also
>> attaching the debug.out file for your info
>>
>> 1 <startup.cpp:109> {0}- Initializing Flexus.
>> 2 <ComponentManager.cpp:81> {0}- Instantiating system with a width
>> factor
>> of: 8
>> 3 <SimicsTracer.cpp:555> {0}- Initializing SimicsTracerManager.
>> 4 <SimicsTracer.cpp:662> {0}- Connecting: cpu0
>> 5 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu0 to
>> Simics object cpu0
>> 6 <SimicsTracer.cpp:662> {0}- Connecting: cpu1
>> 7 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu1 to
>> Simics object cpu1
>> 8 <SimicsTracer.cpp:662> {0}- Connecting: cpu2
>> 9 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu2 to
>> Simics object cpu2
>> 10 <SimicsTracer.cpp:662> {0}- Connecting: cpu3
>> 11 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu3 to
>> Simics object cpu3
>> 12 <SimicsTracer.cpp:662> {0}- Connecting: cpu4
>> 13 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu4 to
>> Simics object cpu4
>> 14 <SimicsTracer.cpp:662> {0}- Connecting: cpu5
>> 15 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu5 to
>> Simics object cpu5
>> 16 <SimicsTracer.cpp:662> {0}- Connecting: cpu6
>> 17 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu6 to
>> Simics object cpu6
>> 18 <SimicsTracer.cpp:662> {0}- Connecting: cpu7
>> 19 <SimicsTracer.cpp:665> {0}- DecoupledFeeder connects Flexus cpu7 to
>> Simics object cpu7
>> 20 <SimicsTracer.cpp:684> {0}- Creating DMA map object
>> 21 <SimicsTracer.cpp:726> {0}- Connecting to DMA memory map
>> 22 <SimicsTracer.cpp:567> {0}- Done initializing SimicsTracerManager.
>> 23 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
>> 24 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
>> 25 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
>> 26 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
>> 27 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
>> 28 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
>> 29 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
>> 30 <BPWarm.hpp:55> {0}- bpwarm port InsnOut is not wired
>> 31 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
>> 32 <FastCache.hpp:69> {0}- L1d port Reads is not wired
>> 33 <FastCache.hpp:69> {0}- L1d port Writes is not wired
>> 34 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
>> 35 <FastCache.hpp:69> {0}- L1d port Reads is not wired
>> 36 <FastCache.hpp:69> {0}- L1d port Writes is not wired
>> 37 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
>> 38 <FastCache.hpp:69> {0}- L1d port Reads is not wired
>> 39 <FastCache.hpp:69> {0}- L1d port Writes is not wired
>> 40 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
>> 41 <FastCache.hpp:69> {0}- L1d port Reads is not wired
>> 42 <FastCache.hpp:69> {0}- L1d port Writes is not wired
>> 43 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
>> 44 <FastCache.hpp:69> {0}- L1d port Reads is not wired
>> 45 <FastCache.hpp:69> {0}- L1d port Writes is not wired
>> 46 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
>> 47 <FastCache.hpp:69> {0}- L1d port Reads is not wired
>> 48 <FastCache.hpp:69> {0}- L1d port Writes is not wired
>> 49 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
>> 50 <FastCache.hpp:69> {0}- L1d port Reads is not wired
>> 51 <FastCache.hpp:69> {0}- L1d port Writes is not wired
>> 52 <FastCache.hpp:69> {0}- L1d port SnoopOut is not wired
>> 53 <FastCache.hpp:69> {0}- L1d port Reads is not wired
>> 54 <FastCache.hpp:69> {0}- L1d port Writes is not wired
>> 55 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
>> 56 <FastCache.hpp:69> {0}- L1i port Reads is not wired
>> 57 <FastCache.hpp:69> {0}- L1i port Writes is not wired
>> 58 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
>> 59 <FastCache.hpp:69> {0}- L1i port Reads is not wired
>> 60 <FastCache.hpp:69> {0}- L1i port Writes is not wired
>> 61 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
>> 62 <FastCache.hpp:69> {0}- L1i port Reads is not wired
>> 63 <FastCache.hpp:69> {0}- L1i port Writes is not wired
>> 64 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
>> 65 <FastCache.hpp:69> {0}- L1i port Reads is not wired
>> 66 <FastCache.hpp:69> {0}- L1i port Writes is not wired
>> 67 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
>> 68 <FastCache.hpp:69> {0}- L1i port Reads is not wired
>> 69 <FastCache.hpp:69> {0}- L1i port Writes is not wired
>> 70 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
>> 71 <FastCache.hpp:69> {0}- L1i port Reads is not wired
>> 72 <FastCache.hpp:69> {0}- L1i port Writes is not wired
>> 73 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
>> 74 <FastCache.hpp:69> {0}- L1i port Reads is not wired
>> 75 <FastCache.hpp:69> {0}- L1i port Writes is not wired
>> 76 <FastCache.hpp:69> {0}- L1i port SnoopOut is not wired
>> 77 <FastCache.hpp:69> {0}- L1i port Reads is not wired
>> 78 <FastCache.hpp:69> {0}- L1i port Writes is not wired
>> 79 <FastCache.hpp:69> {0}- L2 port Reads is not wired
>> 80 <FastCache.hpp:69> {0}- L2 port Writes is not wired
>> 81 <FastCache.hpp:69> {0}- L2 port Reads is not wired
>> 82 <FastCache.hpp:69> {0}- L2 port Writes is not wired
>> 83 <FastCache.hpp:69> {0}- L2 port Reads is not wired
>> 84 <FastCache.hpp:69> {0}- L2 port Writes is not wired
>> 85 <FastCache.hpp:69> {0}- L2 port Reads is not wired
>> 86 <FastCache.hpp:69> {0}- L2 port Writes is not wired
>> 87 <FastCache.hpp:69> {0}- L2 port Reads is not wired
>> 88 <FastCache.hpp:69> {0}- L2 port Writes is not wired
>> 89 <FastCache.hpp:69> {0}- L2 port Reads is not wired
>> 90 <FastCache.hpp:69> {0}- L2 port Writes is not wired
>> 91 <FastCache.hpp:69> {0}- L2 port Reads is not wired
>> 92 <FastCache.hpp:69> {0}- L2 port Writes is not wired
>> 93 <FastCache.hpp:69> {0}- L2 port Reads is not wired
>> 94 <FastCache.hpp:69> {0}- L2 port Writes is not wired
>> 95 <FastBus.hpp:73> {0}- bus port Writes is not wired
>> 96 <FastBus.hpp:73> {0}- bus port Reads is not wired
>> 97 <FastBus.hpp:73> {0}- bus port Evictions is not wired
>> 98 <FastBus.hpp:73> {0}- bus port Flushes is not wired
>> 99 <FastBus.hpp:73> {0}- bus port Invalidations is not wired
>> 100 <wiring.cpp:79> {0}- initializing Parameters...
>> 101 <flexus.cpp:369> {0}- Set stat interval to : 10000000
>> 102 <flexus.cpp:389> {0}- Set profile interval to : 10000000
>> 103 <flexus.cpp:394> {0}- Set timestamp interval to : 1000000
>> 104 <ComponentManager.cpp:96> {0}- Initalizing components...
>> 105 <SimicsTracer.cpp:602> {0}- >>>>> OK
>> 106 <SimicsTracer.cpp:602> {0}- >>>>> OK
>> 107 <SimicsTracer.cpp:602> {0}- >>>>> OK
>> 108 <SimicsTracer.cpp:602> {0}- >>>>> OK
>> 109 <SimicsTracer.cpp:602> {0}- >>>>> OK
>> 110 <SimicsTracer.cpp:602> {0}- >>>>> OK
>> 111 <SimicsTracer.cpp:602> {0}- >>>>> OK
>> 112 <SimicsTracer.cpp:602> {0}- >>>>> OK
>> 113 <flexus.cpp:262> {0}- Timestamp: 2007-May-30 12:36:08
>> 114 <FastCacheImpl.cpp:123> {0}- Running with MT width 1
>> 115 <flexus.cpp:262> {1000000}- Timestamp: 2007-May-30 12:36:30
>> 116 <flexus.cpp:262> {2000000}- Timestamp: 2007-May-30 12:36:53
>> 117 <flexus.cpp:262> {3000000}- Timestamp: 2007-May-30 12:37:16
>> 118 <flexus.cpp:262> {4000000}- Timestamp: 2007-May-30 12:37:39
>> 119 <flexus.cpp:262> {5000000}- Timestamp: 2007-May-30 12:38:02
>> 120 <flexus.cpp:262> {6000000}- Timestamp: 2007-May-30 12:38:25
>> 121 <flexus.cpp:262> {7000000}- Timestamp: 2007-May-30 12:38:47
>> 122 <flexus.cpp:262> {8000000}- Timestamp: 2007-May-30 12:39:10
>> 123 <flexus.cpp:262> {9000000}- Timestamp: 2007-May-30 12:39:33
>> 124 <flexus.cpp:262> {10000000}- Timestamp: 2007-May-30 12:39:55
>> 125 <flexus.cpp:273> {10000000}- Saving stats at: 10000000
>> 126 <flexus.cpp:292> {10000000}- Writing profile at: 10000000
>> 127 <flexus.cpp:262> {11000000}- Timestamp: 2007-May-30 12:40:18
>> 128 <flexus.cpp:262> {12000000}- Timestamp: 2007-May-30 12:40:41
>> 129 <flexus.cpp:262> {13000000}- Timestamp: 2007-May-30 12:41:03
>> 130 <flexus.cpp:262> {14000000}- Timestamp: 2007-May-30 12:41:27
>> 131 <flexus.cpp:262> {15000000}- Timestamp: 2007-May-30 12:41:50
>> 132 <flexus.cpp:262> {16000000}- Timestamp: 2007-May-30 12:42:13
>> 133 <flexus.cpp:262> {17000000}- Timestamp: 2007-May-30 12:42:36
>> 134 <flexus.cpp:262> {18000000}- Timestamp: 2007-May-30 12:42:59
>> 135 <flexus.cpp:262> {19000000}- Timestamp: 2007-May-30 12:43:21
>> 136 <flexus.cpp:262> {20000000}- Timestamp: 2007-May-30 12:43:44
>> 137 <flexus.cpp:273> {20000000}- Saving stats at: 20000000
>> 138 <flexus.cpp:292> {20000000}- Writing profile at: 20000000
>> 139 <flexus.cpp:262> {21000000}- Timestamp: 2007-May-30 12:44:07
>> 140 <flexus.cpp:262> {22000000}- Timestamp: 2007-May-30 12:44:29
>> 141 <flexus.cpp:262> {23000000}- Timestamp: 2007-May-30 12:44:52
>> 142 <flexus.cpp:262> {24000000}- Timestamp: 2007-May-30 12:45:15
>> 143 <flexus.cpp:262> {25000000}- Timestamp: 2007-May-30 12:45:37
>> 144 <flexus.cpp:262> {26000000}- Timestamp: 2007-May-30 12:46:00
>> 145 <flexus.cpp:262> {27000000}- Timestamp: 2007-May-30 12:46:23
>> 146 <flexus.cpp:262> {28000000}- Timestamp: 2007-May-30 12:46:46
>> 147 <flexus.cpp:262> {29000000}- Timestamp: 2007-May-30 12:47:09
>> 148 <flexus.cpp:262> {30000000}- Timestamp: 2007-May-30 12:47:32
>> 149 <flexus.cpp:273> {30000000}- Saving stats at: 30000000
>> 150 <flexus.cpp:292> {30000000}- Writing profile at: 30000000
>> 151 <flexus.cpp:262> {31000000}- Timestamp: 2007-May-30 12:47:56
>> 152 <flexus.cpp:262> {32000000}- Timestamp: 2007-May-30 12:48:19
>> 153 <flexus.cpp:262> {33000000}- Timestamp: 2007-May-30 12:48:42
>> 154 <flexus.cpp:262> {34000000}- Timestamp: 2007-May-30 12:49:05
>> 155 <flexus.cpp:262> {35000000}- Timestamp: 2007-May-30 12:49:28
>> 156 <flexus.cpp:262> {36000000}- Timestamp: 2007-May-30 12:51:54
>> 157 <flexus.cpp:262> {37000000}- Timestamp: 2007-May-30 12:52:17
>> 158 <flexus.cpp:262> {38000000}- Timestamp: 2007-May-30 12:52:40
>> 159 <flexus.cpp:262> {39000000}- Timestamp: 2007-May-30 12:53:03
>> 160 <flexus.cpp:262> {40000000}- Timestamp: 2007-May-30 12:53:24
>> 161 <flexus.cpp:273> {40000000}- Saving stats at: 40000000
>> 162 <flexus.cpp:292> {40000000}- Writing profile at: 40000000
>> 163 <flexus.cpp:262> {41000000}- Timestamp: 2007-May-30 12:53:46
>> 164 <flexus.cpp:262> {42000000}- Timestamp: 2007-May-30 12:54:09
>> 165 <flexus.cpp:262> {43000000}- Timestamp: 2007-May-30 12:54:32
>> 166 <flexus.cpp:262> {44000000}- Timestamp: 2007-May-30 12:54:54
>> 167 <flexus.cpp:262> {45000000}- Timestamp: 2007-May-30 12:55:17
>> 168 <flexus.cpp:262> {46000000}- Timestamp: 2007-May-30 12:55:39
>> 169 <flexus.cpp:262> {47000000}- Timestamp: 2007-May-30 12:56:01
>> 170 <flexus.cpp:262> {48000000}- Timestamp: 2007-May-30 12:56:23
>> 171 <flexus.cpp:262> {49000000}- Timestamp: 2007-May-30 12:56:46
>> 172 <flexus.cpp:262> {50000000}- Timestamp: 2007-May-30 12:57:08
>> 173 <flexus.cpp:273> {50000000}- Saving stats at: 50000000
>> 174 <flexus.cpp:292> {50000000}- Writing profile at: 50000000
>> 175 <flexus.cpp:262> {51000000}- Timestamp: 2007-May-30 12:57:31
>> 176 <flexus.cpp:262> {52000000}- Timestamp: 2007-May-30 12:57:53
>> 177 <flexus.cpp:262> {53000000}- Timestamp: 2007-May-30 12:58:16
>> 178 <flexus.cpp:262> {54000000}- Timestamp: 2007-May-30 12:58:38
>> 179 <flexus.cpp:262> {55000000}- Timestamp: 2007-May-30 12:59:00
>>
>> I ended the simulation here as previously it was running for six days
>> without fininshing. Thanks in advance.
>>
>>
>> Abu Saad Papa
>> http://research.iiit.net/~abu_saad/
>> M.S VLSI
>> IIIT, Hyderabad.
>>
>> "GOD GIVES MAN GETS ........
>> GOD FORGIVES MAN FORGETS...."
>> _______________________________________________
>> SimFlex mailing list
>> [email protected]
>> https://sos.ece.cmu.edu/mailman/listinfo/simflex
>> SimFlex web page: http://www.ece.cmu.edu/~simflex
>>
> _______________________________________________
> SimFlex mailing list
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> https://sos.ece.cmu.edu/mailman/listinfo/simflex
> SimFlex web page: http://www.ece.cmu.edu/~simflex
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