Hi, I am new to Flexus and have some simple points to be clarified. 1) What is the main difference between DSMFlex and CMPFlex? In simics both multiprocessor and multicore (CMP) are logically the same so what is the difference in Flexus.
2) I had run the flexus test application given in the Starting Guide and found it useful. I tried for both UniFlex.OoO and DSMFlex.OoO. And for CMP I tried first by not making any changes to prepare-test-app.simics i.e with a single processor and using TraceCMPFlex instead for TraceFlex. And then I ran the application by changing the number of processors to 8 and again using TraceCMPFlex and CMPFlex.OoO. Now in the first instance there is only a single processor but I got no errors in running CMPFlex.OoO which is multicore simulator. (I don't know its functionality as I am new to Flexus). What is the difference between single processor CMP and eight processor CMP for this particular application. 3) If I want to run my own application or any one of the benchmarks, what is the procedure I should follow? (How to form a .craff file and the directory structure similar to $FLEXUS_ROOT/flexus-test-app and other things etc) Bye, Abu Saad From twenisch at ece.cmu.edu Wed May 23 23:55:30 2007 From: twenisch at ece.cmu.edu (Thomas Wenisch) List-Post: [email protected] Date: Wed May 23 23:55:37 2007 Subject: [Simflex] Difference between DSMFLex and CMPFlex In-Reply-To: <[email protected]> References: <[email protected]> Message-ID: <[email protected]> Hi Abu, Apologies for the delay in our reply - somehow I overlooked your message. On Wed, 16 May 2007, [email protected] wrote: > Hi, > I am new to Flexus and have some simple points to be clarified. > 1) What is the main difference between DSMFlex and CMPFlex? In simics both > multiprocessor and multicore (CMP) are logically the same so what is the > difference in Flexus. DSMFlex simulates a directory-based distributed shared memory machine. That is, each processor has its own cache hierarchy and portion of a global shared memory, and the processor nodes are connected through an interconnection network. CMPFlex simulates a single chip multiprocessor with a shared L2. As you point out, these systems are logically the same (from the point of view of the OS), but have drastically different performance characteristics. > > 2) I had run the flexus test application given in the Starting Guide and > found it useful. I tried for both UniFlex.OoO and DSMFlex.OoO. And for CMP I > tried first by not making any changes to prepare-test-app.simics i.e with a > single processor and using TraceCMPFlex instead for TraceFlex. And then I ran > the application by changing the number of processors to 8 and again using > TraceCMPFlex and CMPFlex.OoO. Now in the first instance there is only a > single processor but I got no errors in running CMPFlex.OoO which is > multicore simulator. (I don't know its functionality as I am new to Flexus). > What is the difference between single processor CMP and eight processor CMP > for this particular application. Changing the number of processors varies the number of CPUs visible to the OS (in Simics). The test application can be run with any number of threads - the number of threads is a command line parameter. If the number of threads does not match the number of CPUs, the effect is the same as in a real machine (CPUs sit idle or threads compete for CPUs). A single-processor CMP is a well-defined system - it uses a CMP-capable cache but has only a single processor. The CMP cache includes extra functionality to maintain coherence among cores, that is unneccessary for a uniprocessor. > > 3) If I want to run my own application or any one of the benchmarks, what is > the procedure I should follow? (How to form a .craff file and the directory > structure similar to $FLEXUS_ROOT/flexus-test-app and other things etc) I suggest you begin by understading how checkpoints work in Simics (a .craff file is part of a Simics checkpoint). The Simics User's guide includes extensive documentation on this. Once you know how to bring your own applications into Simics (without Flexus), then you can worry about how to get it to work with Flexus. Best Regards, -Tom Wenisch Computer Architecture Lab Carnegie Mellon University > > Bye, > Abu Saad > _______________________________________________ > SimFlex mailing list > [email protected] > https://sos.ece.cmu.edu/mailman/listinfo/simflex > SimFlex web page: http://www.ece.cmu.edu/~simflex > From abu_saad at research.iiit.net Thu May 24 01:27:15 2007 From: abu_saad at research.iiit.net (Abu Saad Papa) List-Post: [email protected] Date: Thu May 24 02:41:43 2007 Subject: [Simflex] Difference between DSMFLex and CMPFlex In-Reply-To: <[email protected]> References: <[email protected]> <[email protected]> Message-ID: <[email protected]> Thank You for the reply. I would like to mention one more thing about the test application. I changed the number of processors to 8 and also the threads to 8. And then tried to run it with TraceCMPFlex and CMPFlex.OoO, the application is running for the past six days and is still running as I am writing this post. Does the application take so much time to execute for a 8-processor CMP? If anyone has tried the test application for 8-processor CMP please inform me how long it takes to execute the application. > Hi Abu, > > Apologies for the delay in our reply - somehow I overlooked your message. > > On Wed, 16 May 2007, [email protected] wrote: > >> Hi, >> I am new to Flexus and have some simple points to be clarified. >> 1) What is the main difference between DSMFlex and CMPFlex? In simics >> both >> multiprocessor and multicore (CMP) are logically the same so what is the >> difference in Flexus. > > DSMFlex simulates a directory-based distributed shared memory machine. > That is, each processor has its own cache hierarchy and portion of a > global shared memory, and the processor nodes are connected through an > interconnection network. CMPFlex simulates a single chip multiprocessor > with a shared L2. As you point out, these systems are logically the same > (from the point of view of the OS), but have drastically different > performance characteristics. > >> >> 2) I had run the flexus test application given in the Starting Guide and >> found it useful. I tried for both UniFlex.OoO and DSMFlex.OoO. And for >> CMP I >> tried first by not making any changes to prepare-test-app.simics i.e >> with a >> single processor and using TraceCMPFlex instead for TraceFlex. And then >> I ran >> the application by changing the number of processors to 8 and again >> using >> TraceCMPFlex and CMPFlex.OoO. Now in the first instance there is only a >> single processor but I got no errors in running CMPFlex.OoO which is >> multicore simulator. (I don't know its functionality as I am new to >> Flexus). >> What is the difference between single processor CMP and eight processor >> CMP >> for this particular application. > > Changing the number of processors varies the number of CPUs visible to the > OS (in Simics). The test application can be run with any number of > threads - the number of threads is a command line parameter. If the > number of threads does not match the number of CPUs, the effect is the > same as in a real machine (CPUs sit idle or threads compete for CPUs). > > A single-processor CMP is a well-defined system - it uses a CMP-capable > cache but has only a single processor. The CMP cache includes extra > functionality to maintain coherence among cores, that is unneccessary for > a uniprocessor. > >> >> 3) If I want to run my own application or any one of the benchmarks, >> what is >> the procedure I should follow? (How to form a .craff file and the >> directory >> structure similar to $FLEXUS_ROOT/flexus-test-app and other things etc) > > I suggest you begin by understading how checkpoints work in Simics (a > .craff file is part of a Simics checkpoint). The Simics User's guide > includes extensive documentation on this. Once you know how to bring your > own applications into Simics (without Flexus), then you can worry about > how to get it to work with Flexus. > > Best Regards, > -Tom Wenisch > Computer Architecture Lab > Carnegie Mellon University > >> >> Bye, >> Abu Saad >> _______________________________________________ >> SimFlex mailing list >> [email protected] >> https://sos.ece.cmu.edu/mailman/listinfo/simflex >> SimFlex web page: http://www.ece.cmu.edu/~simflex >> > _______________________________________________ > SimFlex mailing list > [email protected] > https://sos.ece.cmu.edu/mailman/listinfo/simflex > SimFlex web page: http://www.ece.cmu.edu/~simflex > -- Abu Saad Papa http://research.iiit.net/~abu_saad/ M.S VLSI IIIT, Hyderabad. "GOD GIVES MAN GETS ........ GOD FORGIVES MAN FORGETS...." From mrinal at ece.umn.edu Sun May 27 23:29:29 2007 From: mrinal at ece.umn.edu (Mrinal Nath) List-Post: [email protected] Date: Sun May 27 23:29:36 2007 Subject: [Simflex] Read and Fetch Request messages in handle_D_ExtGet Message-ID: <[email protected]> Hi, From what I understand of CMPFlex simulator, handle_D_ExtGet is called to process a Reply coming from main memory to L2. I am surprised that I am actually seeing ReadRequest and FetchRequest messages going into handle_D_ExtGet function. Can someone please tell me how this is possible? What path must have been taken (what sequence of function calls) for this to be possible? Thanks Mrinal From jsmolens+ at ece.cmu.edu Mon May 28 00:17:32 2007 From: jsmolens+ at ece.cmu.edu (Jared C. Smolens) List-Post: [email protected] Date: Mon May 28 00:17:37 2007 Subject: [Simflex] Read and Fetch Request messages in handle_D_ExtGet Message-ID: <1408187342.1180325...@miura> Hi Mrinal, The call to handle_D_* is made based upon the current *state* of the block in L2, regardless of what the actual request type is. The case you're seeing is most likely two cores encountering the same off-chip miss close in time (e.g., the 2nd request reaches the L2 before the reply from memory returns). There is nothing unusual about this. If the message is another request, it is queued for later processing after the actual reply comes. - Jared Excerpts From Mrinal Nath <[email protected]>: [Simflex] Read and Fetch Request me: Mrinal Nath <[email protected]> >Hi, > From what I understand of CMPFlex simulator, handle_D_ExtGet is called >to process a Reply coming from main memory to L2. > >I am surprised that I am actually seeing ReadRequest and FetchRequest >messages going into handle_D_ExtGet function. Can someone please tell me >how this is possible? What path must have been taken (what sequence of >function calls) for this to be possible? > >Thanks >Mrinal
